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G
A. Gerosa, Maniero, A., and Neviani, A., A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers, in ESSCIRC, 2003, vol. 1, pp. 157–160.
A. Gerosa, Novo, A., and Neviani, A., Low-power sensing and digitization of cardiac signals based on sigma-delta conversion, in Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on, 2000, pp. 216 - 218.
A. Gerosa and Neviani, A., A 1.8uW Sigma-Delta Modulator for 8-bit Digitization of Cardiac Signals in Implantable Pacemakers Operating Down to 1.8V, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, vol. 52, pp. 71–76, 2005.
A. Gerosa and Mian, G. A., A low complexity EPR-IV equalizer for hard disk read channels, in Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on, 1999, vol. 2, pp. 1069 -1072 vol.2.
A. Gerosa, Novo, A., Mengalli, A., and Neviani, A., A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker, in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001, vol. 1, pp. 296 -299 vol. 1.
A. Gerosa and Mian, G. A., An Equalizer for Hard Disk Drive Channels, with Low Sensitivity to Sampling Phase Variation, in EUSIPCO-98, 1998, vol. 1, pp. 483–486.
A. Gerosa, Bevilacqua, A., and Neviani, A., A local oscillator for WCDMA band VII based on frequency multiplication, Analog Integrated Circuits and Signal Processing, vol. 72, no. 1, 2012.
A. Gerosa, RUBIN, R., and Neviani, A., A Simplified Analysis of Noise in Switched Capacitor Networks from a Circuit Design Perspective, in ECCTD, 2001, vol. 1, pp. 261–264.
A. Gerosa and Neviani, A., A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER, in ISCAS, 2004, vol. 2, pp. 245–248.
A. Gerosa and Neviani, A., A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V, in ISCAS, 2003, vol. 5, pp. 49–52.
A. Gerosa, Maniero, A., and Neviani, A., A Fully-Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemakers, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 51, pp. 1916–1925, 2004.
A. Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 1030 -1040, 2009.
A. Gerosa, Neviani, A., and Cortelazzo, G. M., A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.
A. Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.
F
A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.
A. Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.
A. Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.
A. Franceschin, Padovan, F., Nonis, R., and Bevilacqua, A., On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 657 - 661, 2018.
E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers, in 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024.
C. Fantozzi, Vangelista, L., Vogrig, D., and Campana, O., SDR implementation of a DVB-T2 transmitter: The core building blocks, in 2011 IEEE International Conference on Consumer Electronics (ICCE), 2011, pp. 391 -392.
D
S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.
S. Dal Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2844 -2852, 2008.
S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.
S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.

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