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Author Title [ Type

] Year

Journal Article

A. Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS”, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.

A. Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., “A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects”, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.

A. Gerosa and Neviani, A., “A 1.8uW Sigma-Delta Modulator for 8-bit Digitization of Cardiac Signals in Implantable Pacemakers Operating Down to 1.8V”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, vol. 52, pp. 71–76, 2005.

A. Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., “A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications”, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.

L. Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., “A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation”, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS”, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.

D. Vogrig, Gerosa, A., Neviani, A., Amat, A. G., Montorsi, G., and Benedetto, S., “A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code”, Solid-State Circuits, IEEE Journal of, vol. 40, pp. 753 - 762, 2005.

L. Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., “A 0.13-μm HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication”, IEEE Journal of Solid-State Circuits, pp. 1-12, 2025.

S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., “A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS”, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.

Conference Paper

M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., “Wideband {2–16GHz} local oscillator generation for short-range radar applications”, in Proceedings of the 2013 ESSCIRC, 2013, pp. 49-52.

A. Gerosa and Neviani, A., “A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V”, in ISCAS, 2003, vol. 5, pp. 49–52.

D. Oloumi, Bevilacqua, A., and Bassi, M., “UWB Radar for High Resolution Breast Cancer Scanning: System, Architectures, and Challenges”, in 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019.

S. D. Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., “UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking”, in Digest of Technical Papers of 2008 IEEE International Solid-State Circuits Conference, 2008, pp. 124 -601.

A. Bevilacqua and Niknejad, A. M., “An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers”, in Digest of Technical Papers of 2004 IEEE International Solid-State Circuits Conference, 2004, pp. 382 - 533 Vol.1.

L. Tomasin and Bevilacqua, A., “A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem”, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

S. Dal Toso, Bevilacqua, A., Gerosa, A., and Neviani, A., “A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks”, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 1903 -1906.

D. Vogrig, Bevilacqua, A., Gerosa, A., and Neviani, A., “A symbol-duty-cycled 440 pJ/b impulse radio receiver with 0.57 aJ sensitivity in 130 nm CMOS”, in Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE, 2015, pp. 243-246.

G. Spiazzi, Marconi, S., and Bevilacqua, A., “Step-Up DC-DC converters combining basic topologies with charge pump”, in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1-6.

A. Gerosa, RUBIN, R., and Neviani, A., “A Simplified Analysis of Noise in Switched Capacitor Networks from a Circuit Design Perspective”, in ECCTD, 2001, vol. 1, pp. 261–264.

F. Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., “A SiGe bipolar VCO for backhaul E-band communication systems”, in Proceedings of the 2012 ESSCIRC, 2012, pp. 402 -405.

F. Padovan, Tiebout, M., Dielacher, F., Bevilacqua, A., and Neviani, A., “SiGe BiCMOS VCO with 27% tuning range for 5G communications”, in 2015 Asia-Pacific Microwave Conference (APMC), 2015, vol. 1, pp. 1-3.

C. Fantozzi, Vangelista, L., Vogrig, D., and Campana, O., “SDR implementation of a DVB-T2 transmitter: The core building blocks”, in 2011 IEEE International Conference on Consumer Electronics (ICCE), 2011, pp. 391 -392.

A. Gerosa, Neviani, A., and Zanoni, E., “A SC Video Filter with Analog-RAM-based Delay Efficient Realization”, in ECCTD, 1999, vol. 2, pp. 1247–1250.

A. Celin and Gerosa, A., “A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior”, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.

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