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Integrated Circuits for Analog and RF µ-Systems
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A. Gerosa
,
Neviani, A.
, and
Cortelazzo, G. M.
,
“
A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters
”
, in
Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on
, 1999, pp. 195 -198.
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A. Gerosa
and
Neviani, A.
,
“
A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V
”
, in
ISCAS
, 2003, vol. 5, pp. 49–52.
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A. Gerosa
,
Elettronica Digitale, Esercizi risolti
. PADOVA: Edizioni Libreria Progetto, 2006, pp. 1–216.
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A. Gerosa
,
Novo, A.
, and
Neviani, A.
,
“
Low-power sensing and digitization of cardiac signals based on sigma-delta conversion
”
, in
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
, 2000, pp. 216 - 218.
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A. Gerosa
and
Mian, G. A.
,
“
An Equalizer for Hard Disk Drive Channels, with Low Sensitivity to Sampling Phase Variation
”
, in
EUSIPCO-98
, 1998, vol. 1, pp. 483–486.
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A. Gerosa
and
Neviani, A.
,
“
A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER
”
, in
ISCAS
, 2004, vol. 2, pp. 245–248.
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