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Title
Type
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Year
]
2002
A. Xotta
,
Vogrig, D.
,
Gerosa, A.
,
Neviani, A.
,
Graell i Amat, A.
,
Montorsi, G.
,
Bruccoleri, M.
, and
Betti, G.
,
“
An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels
”
, in
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
, 2002, vol. 5, p. V-69 - V-72 vol.5.
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2003
M. PERENZONI
,
Gerosa, A.
, and
Neviani, A.
,
“
Analog CMOS Implementation of Gallager’s Interative Decoding algorithm applied to a Block Turbo Code
”
, in
ISCAS
, 2003, vol. 5, pp. 813–816.
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2008
S. Soldà
,
Vogrig, D.
,
Bevilacqua, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
Analog decoding of trellis coded modulation for multi-level flash memories
”
, in
IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008.
, 2008, pp. 744 -747.
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2001
A. Gerosa
,
Novo, A.
, and
Neviani, A.
,
“
An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process
”
, in
Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on
, 2001, pp. 152 -157.
DOI
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2007
A. Vallese
,
Bevilacqua, A.
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS
”
, in
Proc. of IEEE 2007 European Solid State Circuits Conference
, 2007, pp. 139 -142.
DOI
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2005
A. G. I. Amatt
,
Benedetto, S.
,
Montorsi, G.
,
Vogrig, D.
,
Neviani, A.
, and
Gerosa, A.
,
“
An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code
”
, in
Communications, 2005. ICC 2005. 2005 IEEE International Conference on
, 2005, vol. 1, pp. 663 - 667 Vol. 1.
DOI
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2004
A. Graell i Amat
,
Montorsi, G.
,
Benedetto, S.
,
Vogrig, D.
,
Neviani, A.
, and
Gerosa, A.
,
“
An analog turbo decoder for the UMTS standard
”
, in
Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on
, 2004, p. 296.
DOI
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2015
A. Passamani
,
Ponton, D.
,
Knoblinger, G.
, and
Bevilacqua, A.
,
“
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs
”
, in
Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015
, 2015, pp. 1-4.
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2020
S. Veni
,
Andreani, P.
,
Caruso, M.
,
Tiebout, M.
, and
Bevilacqua, A.
,
“
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
”
,
IEEE Journal of Solid-State Circuits
, vol. 55, pp. 2345-2355, 2020.
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2022
A. Bettini
,
Cosnier, T.
,
Magnani, A.
,
Syshchyk, O.
,
Borga, M.
,
Decoutere, S.
, and
Neviani, A.
,
“
Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology
”
, in
2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
, 2022.
DOI
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2009
M. Camponeschi
,
Bevilacqua, A.
, and
Andreani, P.
,
“
Analysis and design of a low-power single-stage CMOS wireless receiver
”
, in
Proc. of 2009 NORCHIP
, 2009, pp. 1 -4.
DOI
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A. Vallese
,
Bevilacqua, A.
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems
”
,
IEEE Journal of Solid-State Circuits
, vol. 44, pp. 331 -343, 2009.
DOI
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2024
A. Iesurum
,
Manente, D.
,
Padovan, F.
,
Bassi, M.
, and
Bevilacqua, A.
,
“
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
”
,
IEEE Journal of Solid-State Circuits
, vol. 59, pp. 294-306, 2024.
DOI
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2016
A. Passamani
,
Ponton, D.
,
Knoblinger, G.
, and
Bevilacqua, A.
,
“
Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers
”
,
Analog Integrated Circuits and Signal Processing
, vol. 89, no. 2, pp. 307-315, 2016.
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2023
L. Tomasin
,
Vogrig, D.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters
”
,
IEEE Transactions on Microwave Theory and Techniques
, pp. 1-12, 2023.
DOI
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2012
A. Bevilacqua
and
Andreani, P.
,
“
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
”
,
Circuits and Systems I: Regular Papers, IEEE Transactions on
, vol. 59, pp. 938 -945, 2012.
DOI
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2024
L. Bellemo
and
Bevilacqua, A.
,
“
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
”
,
IEEE Transactions on Circuits and Systems II: Express Briefs
, pp. 1-1, 2024.
DOI
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2011
A. Bevilacqua
and
Andreani, P.
,
“
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory
”
, in
2011 IEEE International Symposium on Circuits and Systems (ISCAS)
, 2011, pp. 217 -220.
DOI
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2022
F. Quadrelli
,
Manente, D.
,
Seebacher, D.
,
Padovan, F.
,
Bassi, M.
,
Mazzanti, A.
, and
Bevilacqua, A.
,
“
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
”
,
IEEE Journal of Solid-State Circuits
, vol. 57, pp. 1968-1981, 2022.
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2017
P. Scaramuzza
,
Rubino, C.
,
Tiebout, M.
,
Caruso, M.
,
Ortner, M.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems
”
, in
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
, 2017, pp. 187-190.
DOI
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2018
P. Scaramuzza
,
Rubino, C.
,
Caruso, M.
,
Tiebout, M.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 65, no. 11, pp. 3780 - 3789, 2018.
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2000
A. Novo
,
Gerosa, A.
,
Neviani, A.
,
Mozzi, A.
, and
Zanoni, E.
,
“
A CMOS 0.8 um programmable charge pump for the output stage of an implantable pacemaker
”
, in
Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on
, 2000, pp. 34/1 -34/5.
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2001
A. Xotta
,
Gerosa, A.
, and
Neviani, A.
,
“
CMOS implementation of all-analogue APP decoders: analysis of performances and limitations
”
,
Electronics Letters
, vol. 37, pp. 1501 -1503, 2001.
DOI
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2015
A. Bevilacqua
,
“
CMOS UWB Transceivers for Short-Range Microwave Medical Imaging
”
, in
Wireless transceiver circuits
, Boca Raton: CRC Press, Taylor & Francis group, 2015, pp. 305–333.
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2022
N. Modolo
,
De Santi, C.
,
Baratella, G.
,
Bettini, A.
,
Borga, M.
,
Posthuma, N.
,
Bakeroot, B.
,
You, S.
,
Decoutere, S.
,
Bevilacqua, A.
,
Neviani, A.
,
MENEGHESSO, G.
,
Zanoni, E.
, and
Meneghini, M.
,
“
Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices
”
,
IEEE Transactions on Electron Devices
, pp. 1-6, 2022.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
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