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Author Title [ Type

] Year

Journal Article

N. Modolo, De Santi, C., Baratella, G., Bettini, A., Borga, M., Posthuma, N., Bakeroot, B., You, S., Decoutere, S., Bevilacqua, A., Neviani, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., “Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices”, IEEE Transactions on Electron Devices, pp. 1-6, 2022.

A. Xotta, Gerosa, A., and Neviani, A., “CMOS implementation of all-analogue APP decoders: analysis of performances and limitations”, Electronics Letters, vol. 37, pp. 1501 -1503, 2001.

P. Scaramuzza, Rubino, C., Caruso, M., Tiebout, M., Bevilacqua, A., and Neviani, A., “Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3780 - 3789, 2018.

F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

L. Bellemo and Bevilacqua, A., “On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 3715-3719, 2024.

A. Bevilacqua and Mazzanti, A., “Analysis of CMRR in Doubly-Tuned Transformer Baluns”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4874-4878, 2024.

A. Bevilacqua and Andreani, P., “An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators”, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, pp. 938 -945, 2012.

L. Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., “Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters”, IEEE Transactions on Microwave Theory and Techniques, vol. 72, pp. 2840-2851, 2024.

A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., “Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers”, Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 307-315, 2016.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs”, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., “Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems”, IEEE Journal of Solid-State Circuits, vol. 44, pp. 331 -343, 2009.

D. Pecile, Gambarucci, A., Kokorovic, S., and Bevilacqua, A., “Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm P SAT and 40.1% PAE”, IEEE Transactions on Microwave Theory and Techniques, pp. 1-12, 2025.

S. Veni, Andreani, P., Caruso, M., Tiebout, M., and Bevilacqua, A., “Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO”, IEEE Journal of Solid-State Circuits, vol. 55, pp. 2345-2355, 2020.

A. Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., “An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner”, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., “A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer”, IEEE Journal of Solid-State Circuits, vol. 48, pp. 1741-1750, 2013.

S. Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., “A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.

S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., “A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13um CMOS”, IEEE Journal of Solid-State Circuits, vol. 46, pp. 1636 -1647, 2011.

M. Bassi, Zhao, J., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., “A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP”, IEEE Journal of Solid-State Circuits, vol. 50, pp. 1618-1628, 2015.

M. Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., “A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.

A. D. Capobianco, Khan, M. S., Caruso, M., and Bevilacqua, A., “3-18 GHz compact planar antenna for short-range radar imaging”, Electronics Letters, vol. 50, pp. 1016-1018, 2014.

A. Gerosa, Cortelazzo, G. M., Baschirotto, A., and Malavasi, E., “2D video rate SC FIR filters based on analog RAMs”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 46, pp. 1348 -1360, 1999.

D. Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., “A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.

A. Bevilacqua and Andreani, P., “A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2”, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, pp. 1–10, 2012.

M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., “A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 413-422, 2015.

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