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D
S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.
S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.
S. Dal Toso, Bevilacqua, A., Gerosa, A., and Neviani, A., A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 1903 -1906.
S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands S Through Ku, IEEE Transactions on Microwave Theory and Techniques, vol. 58, pp. 1686 -1695, 2010.
S. Dal Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2844 -2852, 2008.
S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.
G
A. Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.
A. Gerosa, Novo, A., and Neviani, A., An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.
A. Gerosa, Costa, M. D., Bevilacqua, A., Vogrig, D., and Neviani, A., An energy-detector for non-coherent impulse-radio UWB receivers, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008, 2008, pp. 2705 -2708.
A. Gerosa, Bevilacqua, A., Neviani, A., and Xotta, A., An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter, in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, 2006, p. 4 pp.
A. Gerosa, Xotta, A., Neviani, A., and Mian, G. A., Frequency Offset Compensation in Fractionally Spaced Equalization, IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS, vol. 150, pp. 134–140, 2003.
A. Gerosa, Elettronica Digitale, Esercizi risolti. PADOVA: Edizioni Libreria Progetto, 2006, pp. 1–216.
A. Gerosa, A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 949 -952 vol.2.
A. Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.

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