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2006

A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., “A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO”, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

A. Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., “An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.

A. Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., Neviani, A., and Gerosa, A., “CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code”, in Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE, 2006, pp. 1 -6.

A. Graell i Amat, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., “Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code”, Communications, IEEE Transactions on, vol. 54, pp. 1973 -1982, 2006.

A. Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., “A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers”, IEEE Microwave and Wireless Components Letters, vol. 16, pp. 134 -136, 2006.

A. Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., SOLDA, S., Neviani, A., and Gerosa, A., “Iterative Analog Decoder for a SCCC”, in Analog Decoding Workshop, 2006.

A. Maniero, Bevilacqua, A., Gerosa, A., and Neviani, A., “A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency”, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 90 -93.

A. Gerosa, Bevilacqua, A., Neviani, A., and Xotta, A., “An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter”, in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, 2006, p. 4 pp.

2005

D. Vogrig, Gerosa, A., Neviani, A., Amat, A. G., Montorsi, G., and Benedetto, S., “A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code”, Solid-State Circuits, IEEE Journal of, vol. 40, pp. 753 - 762, 2005.

D. Vogrig, Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., and Benedetto, S., “A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code”, in Research in Microelectronics and Electronics, 2005 PhD, 2005, vol. 1, pp. 31 - 34 vol.1.

A. Gerosa and Neviani, A., “A 1.8uW Sigma-Delta Modulator for 8-bit Digitization of Cardiac Signals in Implantable Pacemakers Operating Down to 1.8V”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, vol. 52, pp. 71–76, 2005.

A. G. I. Amatt, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., “An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code”, in Communications, 2005. ICC 2005. 2005 IEEE International Conference on, 2005, vol. 1, pp. 663 - 667 Vol. 1.

A. Xotta, Gerosa, A., and Neviani, A., “A Multi-Mode Sigma-Delta Analog-to-Digital Converter for GSM, UMTS and WLAN”, in ISCAS, 2005.

2004

A. Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., “An analog turbo decoder for the UMTS standard”, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.

A. Gerosa, Maniero, A., and Neviani, A., “A Fully-Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemakers”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 51, pp. 1916–1925, 2004.

A. Gerosa, Neviani, A., and Maniero, A., “A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, pp. 1083–1093, 2004.

A. Gerosa and Neviani, A., “A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER”, in ISCAS, 2004, vol. 2, pp. 245–248.

A. Xotta, Gerosa, A., and Neviani, A., “A Programmable-Order Sigma-Delta Converter for a Multi-Standard Wireless Receiver”, in WowCas, Vancouver B.C., Canada, 2004, vol. 1, pp. 33–34.

2003

M. PERENZONI, Gerosa, A., and Neviani, A., “Analog CMOS Implementation of Gallager’s Interative Decoding algorithm applied to a Block Turbo Code”, in ISCAS, 2003, vol. 5, pp. 813–816.

A. Gerosa and Neviani, A., “Enhancing Output Voltage Swing in Low-Voltage Micro-Power OTA Using Self-Cascode”, ELECTRONICS LETTERS, vol. 39, pp. 638–639, 2003.

A. Gerosa, Xotta, A., Neviani, A., and Mian, G. A., “Frequency Offset Compensation in Fractionally Spaced Equalization”, IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS, vol. 150, pp. 134–140, 2003.

A. Gerosa, Maniero, A., and Neviani, A., “A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers”, in ESSCIRC, 2003, vol. 1, pp. 157–160.

A. Maniero, Gerosa, A., and Neviani, A., “Performance Optimization in Micro-Power, Low-Voltage, Log-Domain Filters in Pure CMOS Technology”, in ISCAS, 2003, vol. 1, pp. 565–568.

A. Gerosa and Neviani, A., “A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V”, in ISCAS, 2003, vol. 5, pp. 49–52.

2002

A. Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., “An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels”, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.

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