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B

A. Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., “A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers”, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.

A. Bevilacqua and Svelto, F., “Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, pp. 117 - 121, 2005.

A. Bevilacqua, Camponeschi, M., Tiebout, M., Gerosa, A., and Neviani, A., “Design of broadband inductorless LNAs in ultra-scaled CMOS technologies”, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008. , 2008, pp. 1300 -1303.

A. Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., “A 0.35 um SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection”, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 1015 -1018.

A. Bevilacqua, “CMOS UWB Transceivers for Short-Range Microwave Medical Imaging”, in Wireless transceiver circuits, Boca Raton: CRC Press, Taylor & Francis group, 2015, pp. 305–333.

A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., “Transformer-Based Dual-Mode Voltage-Controlled Oscillators”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, pp. 293 -297, 2007.

A. Bevilacqua and Mazzanti, A., “Analysis of CMRR in Doubly-Tuned Transformer Baluns”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4874-4878, 2024.

A. Bevilacqua and Andreani, P., “A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2”, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, pp. 1–10, 2012.

A. Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., “An Integrated Solution for Suppressing WLAN Signals in UWB Receivers”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, pp. 1617 -1625, 2007.

A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., “A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO”, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

A. Bevilacqua and Niknejad, A. M., “An Ultrawideband CMOS Low-Noise Amplifier for 3.1–10.6-GHz Wireless Receivers”, IEEE Journal of Solid-State Circuits, vol. 39, pp. 2259–2268, 2004.

A. Bevilacqua and Andreani, P., “A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2”, in NORCHIP, 2011, 2011, pp. 1 -4.

A. Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., “Quadrature VCOs Based on Coupled PLLs”, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 2140 -2143.

A. Bevilacqua and Mazzanti, A., “On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators”, IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1-10, 2025.

A. Bilato, Issakov, V., and Bevilacqua, A., “Considerations on 120GHz LO Signal Generation and Distribution for Highly-Integrated Multi-Channel Radar Transceivers”, in 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019.

A. Bilato, Issakov, V., Mazzanti, A., and Bevilacqua, A., “A Multichannel D-Band Radar Receiver With Optimized LO Distribution”, IEEE Solid-State Circuits Letters, vol. 4, pp. 141-144, 2021.

A. Bilato, Issakov, V., and Bevilacqua, A., “A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS”, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

J. Borremans, Bevilacqua, A., Bronckers, S., Dehan, M., Kuijk, M., Wambacq, P., and Craninckx, J., “A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2693 -2705, 2008.

F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., “A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset”, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.

S. Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., “A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner”, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

C

M. Camponeschi, Bevilacqua, A., Tiebout, M., and Neviani, A., “A X-Band I/Q Upconverter in 65 nm CMOS for High Resolution FMCW Radars”, IEEE Microwave and Wireless Components Letters, vol. 22, pp. 141 -143, 2012.

M. Camponeschi, Bevilacqua, A., Neviani, A., and Andreani, P., “Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end”, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2063 -2066.

M. Camponeschi, Bevilacqua, A., and Andreani, P., “Analysis and design of a low-power single-stage CMOS wireless receiver”, in Proc. of 2009 NORCHIP, 2009, pp. 1 -4.

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