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Journal Article
A. Bevilacqua, Fundamentals of Integrated Transformers: From Principles to Applications, IEEE Solid-State Circuits Magazine, vol. 12, pp. 86-100, 2020.
A. Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers, IEEE Microwave and Wireless Components Letters, vol. 16, pp. 134 -136, 2006.
S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.
A. Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 1030 -1040, 2009.
A. Bevilacqua and Mazzanti, A., Doubly-Tuned Transformer Networks: A Tutorial, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, pp. 550-555, 2021.
F. Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.
D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 607-617, 2023.
J. Borremans, Bevilacqua, A., Bronckers, S., Dehan, M., Kuijk, M., Wambacq, P., and Craninckx, J., A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2693 -2705, 2008.
N. Modolo, De Santi, C., Baratella, G., Bettini, A., Borga, M., Posthuma, N., Bakeroot, B., You, S., Decoutere, S., Bevilacqua, A., Neviani, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices, IEEE Transactions on Electron Devices, pp. 1-6, 2022.
P. Scaramuzza, Rubino, C., Caruso, M., Tiebout, M., Bevilacqua, A., and Neviani, A., Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3780 - 3789, 2018.
F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.
L. Bellemo and Bevilacqua, A., On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband, IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, 2024.
A. Bevilacqua and Andreani, P., An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, pp. 938 -945, 2012.
L. Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters, IEEE Transactions on Microwave Theory and Techniques, pp. 1-12, 2023.
A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers, Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 307-315, 2016.
A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.
A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems, IEEE Journal of Solid-State Circuits, vol. 44, pp. 331 -343, 2009.
S. Veni, Andreani, P., Caruso, M., Tiebout, M., and Bevilacqua, A., Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO, IEEE Journal of Solid-State Circuits, vol. 55, pp. 2345-2355, 2020.
A. Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.
M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer, IEEE Journal of Solid-State Circuits, vol. 48, pp. 1741-1750, 2013.
S. Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.
S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13um CMOS, IEEE Journal of Solid-State Circuits, vol. 46, pp. 1636 -1647, 2011.
M. Bassi, Zhao, J., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP, IEEE Journal of Solid-State Circuits, vol. 50, pp. 1618-1628, 2015.
M. Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.

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