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Integrated Circuits for Analog and RF µ-Systems
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Conference Paper
A. Gerosa
and
Neviani, A.
,
“
A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V
”
, in
ISCAS
, 2003, vol. 5, pp. 49–52.
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Recent Publications
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
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