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Integrated Circuits for Analog and RF µ-Systems
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2018
A. Mazzanti
and
Bevilacqua, A.
,
“
Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 65, no. 12, pp. 4157 - 4168, 2018.
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2017
D. Vogrig
,
Bevilacqua, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
A Symbol-Duty-Cycled 440-pJ/b Impulse Radio Receiver With 0.57-aJ Sensitivity in 130-nm CMOS
”
,
IEEE Transactions on Microwave Theory and Techniques
, vol. 65, pp. 565-573, 2017.
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2016
G. Spiazzi
,
Marconi, S.
, and
Bevilacqua, A.
,
“
Step-Up DC-DC converters combining basic topologies with charge pump
”
, in
2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL)
, 2016, pp. 1-6.
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2015
F. Padovan
,
Tiebout, M.
,
Dielacher, F.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
SiGe BiCMOS VCO with 27% tuning range for 5G communications
”
, in
2015 Asia-Pacific Microwave Conference (APMC)
, 2015, vol. 1, pp. 1-3.
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D. Vogrig
,
Bevilacqua, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
A symbol-duty-cycled 440 pJ/b impulse radio receiver with 0.57 aJ sensitivity in 130 nm CMOS
”
, in
Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE
, 2015, pp. 243-246.
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2012
F. Padovan
,
Tiebout, M.
,
Mertens, K.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
A SiGe bipolar VCO for backhaul E-band communication systems
”
, in
Proceedings of the 2012 ESSCIRC
, 2012, pp. 402 -405.
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2011
C. Fantozzi
,
Vangelista, L.
,
Vogrig, D.
, and
Campana, O.
,
“
SDR implementation of a DVB-T2 transmitter: The core building blocks
”
, in
2011 IEEE International Conference on Consumer Electronics (ICCE)
, 2011, pp. 391 -392.
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2005
A. Bevilacqua
and
Svelto, F.
,
“
Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers
”
,
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol. 52, pp. 117 - 121, 2005.
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2001
A. Gerosa
,
RUBIN, R.
, and
Neviani, A.
,
“
A Simplified Analysis of Noise in Switched Capacitor Networks from a Circuit Design Perspective
”
, in
ECCTD
, 2001, vol. 1, pp. 261–264.
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A. Novo
,
Gerosa, A.
, and
Neviani, A.
,
“
A Sub-Micron CMOS Programmable Charge Pump for Implantable Pacemaker
”
,
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
, vol. 27, pp. 211–217, 2001.
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1999
A. Gerosa
,
Neviani, A.
, and
Zanoni, E.
,
“
A SC Video Filter with Analog-RAM-based Delay Efficient Realization
”
, in
ECCTD
, 1999, vol. 2, pp. 1247–1250.
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Recent Publications
A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS
A Reconfigurable Switched Capacitor DC–DC Converter With 1.9–6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects
Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters
More...