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A. Gerosa, Neviani, A., and Cortelazzo, G. M., A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.
A. Maniero, Gerosa, A., and Neviani, A., Performance Optimization in Micro-Power, Low-Voltage, Log-Domain Filters in Pure CMOS Technology, in ISCAS, 2003, vol. 1, pp. 565–568.
A. Bevilacqua and Andreani, P., Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, pp. 20 -24, 2012.
A. Mazzanti and Bevilacqua, A., On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 2334-2341, 2015.
A. Novo, Gerosa, A., Neviani, A., Mozzi, A., and Zanoni, E., Programmable voltage multiplier for pacemaker output pulse generation, Electronics Letters, vol. 35, pp. 560 -561, 1999.
A. Novo, Gerosa, A., Neviani, A., Zanoni, E., and Mozzi, A., Programmable voltage multipliers for pacemaker output pulse generation in CMOS 0.8 um technology, in Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European, 1999, pp. 386 - 389.
A. Xotta, Gerosa, A., and Neviani, A., A Programmable-Order Sigma-Delta Converter for a Multi-Standard Wireless Receiver, in WowCas, Vancouver B.C., Canada, 2004, vol. 1, pp. 33–34.