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Integrated Circuits for Analog and RF µ-Systems
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2001
A. Gerosa
,
“
Design of Power-Optimized OTAs for SC Applications
”
. 2001.
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2006
A. Graell i Amat
,
Benedetto, S.
,
Montorsi, G.
,
Vogrig, D.
,
Neviani, A.
, and
Gerosa, A.
,
“
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code
”
,
Communications, IEEE Transactions on
, vol. 54, pp. 1973 -1982, 2006.
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2008
A. Bevilacqua
,
Camponeschi, M.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
Design of broadband inductorless LNAs in ultra-scaled CMOS technologies
”
, in
IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008.
, 2008, pp. 1300 -1303.
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2010
A. Gerosa
,
Soldà, S.
,
Bevilacqua, A.
,
Vogrig, D.
, and
Neviani, A.
,
“
A digitally programmable ring oscillator in the UWB range
”
, in
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),
, 2010, pp. 1101 -1104.
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2015
F. Padovan
,
Tiebout, M.
,
Mertens, K. L. R.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 62, pp. 607-615, 2015.
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2021
A. Bevilacqua
and
Mazzanti, A.
,
“
Doubly-Tuned Transformer Networks: A Tutorial
”
,
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol. 68, pp. 550-555, 2021.
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Recent Publications
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
Doubly-Tuned Transformer Networks: A Tutorial
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