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Integrated Circuits for Analog and RF µ-Systems
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Bevilacqua, A.
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2024
A. Iesurum
,
Manente, D.
,
Padovan, F.
,
Bassi, M.
, and
Bevilacqua, A.
,
“
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
”
,
IEEE Journal of Solid-State Circuits
, vol. 59, pp. 294-306, 2024.
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2023
L. Tomasin
,
Vogrig, D.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters
”
,
IEEE Transactions on Microwave Theory and Techniques
, pp. 1-12, 2023.
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2020
S. Veni
,
Andreani, P.
,
Caruso, M.
,
Tiebout, M.
, and
Bevilacqua, A.
,
“
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
”
,
IEEE Journal of Solid-State Circuits
, vol. 55, pp. 2345-2355, 2020.
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2016
A. Passamani
,
Ponton, D.
,
Knoblinger, G.
, and
Bevilacqua, A.
,
“
Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers
”
,
Analog Integrated Circuits and Signal Processing
, vol. 89, no. 2, pp. 307-315, 2016.
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2015
A. Passamani
,
Ponton, D.
,
Knoblinger, G.
, and
Bevilacqua, A.
,
“
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs
”
, in
Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015
, 2015, pp. 1-4.
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2012
A. Bevilacqua
and
Andreani, P.
,
“
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
”
,
Circuits and Systems I: Regular Papers, IEEE Transactions on
, vol. 59, pp. 938 -945, 2012.
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2010
M. Camponeschi
,
Bevilacqua, A.
,
Neviani, A.
, and
Andreani, P.
,
“
Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end
”
, in
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS)
, 2010, pp. 2063 -2066.
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2009
M. Camponeschi
,
Bevilacqua, A.
, and
Andreani, P.
,
“
Analysis and design of a low-power single-stage CMOS wireless receiver
”
, in
Proc. of 2009 NORCHIP
, 2009, pp. 1 -4.
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A. Vallese
,
Bevilacqua, A.
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems
”
,
IEEE Journal of Solid-State Circuits
, vol. 44, pp. 331 -343, 2009.
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2008
S. Soldà
,
Vogrig, D.
,
Bevilacqua, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
Analog decoding of trellis coded modulation for multi-level flash memories
”
, in
IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008.
, 2008, pp. 744 -747.
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2007
A. Vallese
,
Bevilacqua, A.
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS
”
, in
Proc. of IEEE 2007 European Solid State Circuits Conference
, 2007, pp. 139 -142.
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2006
A. Gerosa
,
Xotta, A.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 53, pp. 2109 -2124, 2006.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
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