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Integrated Circuits for Analog and RF µ-Systems
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low-noise amplifier
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A. Bevilacqua
,
Sandner, C.
,
Gerosa, A.
, and
Neviani, A.
,
“
A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers
”
,
IEEE Microwave and Wireless Components Letters
, vol. 16, pp. 134 -136, 2006.
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A
A. Vallese
,
Bevilacqua, A.
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems
”
,
IEEE Journal of Solid-State Circuits
, vol. 44, pp. 331 -343, 2009.
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M. Camponeschi
,
Bevilacqua, A.
, and
Andreani, P.
,
“
Analysis and design of a low-power single-stage CMOS wireless receiver
”
, in
Proc. of 2009 NORCHIP
, 2009, pp. 1 -4.
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6
A. Bevilacqua
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS
”
, in
IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008.
, 2008, vol. 1, pp. 25 -28.
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0
A. Bevilacqua
,
Maniero, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 0.35 um SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection
”
, in
13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06.
, 2006, pp. 1015 -1018.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
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