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Integrated Circuits for Analog and RF µ-Systems
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Frequency measurement
and
Author
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Bevilacqua, A.
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2019
M. Bassi
,
Boi, G.
,
Padovan, F.
,
Fritzin, J.
,
Di Martino, S.
,
Knauder, D.
, and
Bevilacqua, A.
,
“
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS
”
,
IEEE Solid-State Circuits Letters
, vol. 2, pp. 107-110, 2019.
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2017
A. Passamani
,
Ponton, D.
,
Thaller, E.
,
Knoblinger, G.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE
”
, in
2017 IEEE International Solid-State Circuits Conference (ISSCC)
, 2017, pp. 232-233.
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2016
F. Padovan
,
Tiebout, M.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers
”
, in
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
, 2016, pp. 363-366.
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2015
F. Padovan
,
Tiebout, M.
,
Dielacher, F.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
SiGe BiCMOS VCO with 27% tuning range for 5G communications
”
, in
2015 Asia-Pacific Microwave Conference (APMC)
, 2015, vol. 1, pp. 1-3.
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2014
M. Caruso
,
Bevilacqua, A.
, and
Neviani, A.
,
“
An X-Band Lumped-Element Wilkinson Combiner With Embedded Impedance Transformation
”
,
IEEE Microwave and Wireless Components Letters
, vol. 24, pp. 689-691, 2014.
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2012
F. Padovan
,
Tiebout, M.
,
Mertens, K.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
A SiGe bipolar VCO for backhaul E-band communication systems
”
, in
Proceedings of the 2012 ESSCIRC
, 2012, pp. 402 -405.
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Recent Publications
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS
A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
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