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voltage-controlled oscillators
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Bevilacqua, A.
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2024
A. Iesurum
,
Manente, D.
,
Padovan, F.
,
Bassi, M.
, and
Bevilacqua, A.
,
“
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
”
,
IEEE Journal of Solid-State Circuits
, vol. 59, pp. 294-306, 2024.
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2019
A. Franceschin
,
Andreani, P.
,
Padovan, F.
,
Bassi, M.
,
Nonis, R.
, and
Bevilacqua, A.
,
“
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion
”
, in
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)
, 2019.
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2018
F. Padovan
,
Quadrelli, F.
,
Bassi, M.
,
Tiebout, M.
, and
Bevilacqua, A.
,
“
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations
”
, in
2018 IEEE International Solid - State Circuits Conference - (ISSCC)
, 2018.
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2017
F. Boscolo
,
Padovan, F.
,
Quadrelli, F.
,
Tiebout, M.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset
”
, in
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
, 2017, pp. 91-94.
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2015
F. Padovan
,
Tiebout, M.
,
Mertens, K. L. R.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 62, pp. 607-615, 2015.
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F. Padovan
,
Tiebout, M.
,
Dielacher, F.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
SiGe BiCMOS VCO with 27% tuning range for 5G communications
”
, in
2015 Asia-Pacific Microwave Conference (APMC)
, 2015, vol. 1, pp. 1-3.
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2012
F. Padovan
,
Tiebout, M.
,
Mertens, K.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
A SiGe bipolar VCO for backhaul E-band communication systems
”
, in
Proceedings of the 2012 ESSCIRC
, 2012, pp. 402 -405.
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2010
S. Dal Toso
,
Bevilacqua, A.
,
Tiebout, M.
,
Da Dalt, N.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS
”
,
IEEE Journal of Solid-State Circuits
, vol. 45, pp. 1295 -1304, 2010.
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2009
S. Dal Toso
,
Bevilacqua, A.
,
Tiebout, M.
,
Da Dalt, N.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS
”
, in
Proceedings of ESSCIRC 2009
, 2009, pp. 444 -447.
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2008
J. Borremans
,
Bevilacqua, A.
,
Bronckers, S.
,
Dehan, M.
,
Kuijk, M.
,
Wambacq, P.
, and
Craninckx, J.
,
“
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS
”
,
IEEE Journal of Solid-State Circuits
, vol. 43, pp. 2693 -2705, 2008.
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2007
A. Bevilacqua
,
Sandner, C.
,
Gerosa, A.
, and
Neviani, A.
,
“
Quadrature VCOs Based on Coupled PLLs
”
, in
IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007
, 2007, pp. 2140 -2143.
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A. Bevilacqua
,
Pavan, F. P.
,
Sandner, C.
,
Gerosa, A.
, and
Neviani, A.
,
“
Transformer-Based Dual-Mode Voltage-Controlled Oscillators
”
,
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol. 54, pp. 293 -297, 2007.
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2006
A. Bevilacqua
,
Pavan, F. P.
,
Sandner, C.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO
”
, in
Proceedings of the 32nd European Solid-State Circuits Conference
, 2006, pp. 440 -443.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
More...