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Conference Paper
S. Veni, Caruso, M., Tiebout, M., and Bevilacqua, A., A 17 GHz All-npn Push-Pull Class-C VCO, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.
F. Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.
A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.
F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.
A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.
A. Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.
F. Padovan, Quadrelli, F., Bassi, M., Tiebout, M., and Bevilacqua, A., A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations, in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.
F. Padovan, Tiebout, M., Dielacher, F., Bevilacqua, A., and Neviani, A., SiGe BiCMOS VCO with 27% tuning range for 5G communications, in 2015 Asia-Pacific Microwave Conference (APMC), 2015, vol. 1, pp. 1-3.
F. Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., A SiGe bipolar VCO for backhaul E-band communication systems, in Proceedings of the 2012 ESSCIRC, 2012, pp. 402 -405.
Journal Article
M. Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.
A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.
L. Bellemo and Bevilacqua, A., On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband, IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, 2024.
F. Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.
A. Franceschin, Padovan, F., Nonis, R., and Bevilacqua, A., On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 657 - 661, 2018.
A. Mazzanti and Bevilacqua, A., On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 2334-2341, 2015.
F. Pepe, Bevilacqua, A., and Andreani, P., On the Remarkable Performance of the Series-Resonance CMOS Oscillator, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 531-542, 2018.