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Integrated Circuits for Analog and RF µ-Systems
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voltage 1.2 V
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Bevilacqua, A.
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2019
A. Gatti
,
Spiazzi, G.
,
Gerosa, A.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications
”
,
IEEE Solid-State Circuits Letters
, vol. 2, pp. 211-214, 2019.
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2010
S. Dal Toso
,
Bevilacqua, A.
,
Tiebout, M.
,
Da Dalt, N.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS
”
,
IEEE Journal of Solid-State Circuits
, vol. 45, pp. 1295 -1304, 2010.
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A. Bevilacqua
,
Lorenzon, L.
,
Da Dalt, N.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS
”
, in
Proceedings of the ESSCIRC 2010
, 2010, pp. 150 -153.
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2009
S. Dal Toso
,
Bevilacqua, A.
,
Tiebout, M.
,
Da Dalt, N.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS
”
, in
Proceedings of ESSCIRC 2009
, 2009, pp. 444 -447.
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2008
J. Borremans
,
Bevilacqua, A.
,
Bronckers, S.
,
Dehan, M.
,
Kuijk, M.
,
Wambacq, P.
, and
Craninckx, J.
,
“
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS
”
,
IEEE Journal of Solid-State Circuits
, vol. 43, pp. 2693 -2705, 2008.
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S. Dal Toso
,
Bevilacqua, A.
,
Tiebout, M.
,
Marsili, S.
,
Sandner, C.
,
Gerosa, A.
, and
Neviani, A.
,
“
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking
”
,
IEEE Journal of Solid-State Circuits
, vol. 43, pp. 2844 -2852, 2008.
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2006
A. Maniero
,
Bevilacqua, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency
”
, in
13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06.
, 2006, pp. 90 -93.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
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