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Integrated Circuits for Analog and RF µ-Systems
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Bevilacqua, A.
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2024
A. Iesurum
,
Manente, D.
,
Padovan, F.
,
Bassi, M.
, and
Bevilacqua, A.
,
“
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
”
,
IEEE Journal of Solid-State Circuits
, vol. 59, pp. 294-306, 2024.
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2019
M. Bassi
,
Boi, G.
,
Padovan, F.
,
Fritzin, J.
,
Di Martino, S.
,
Knauder, D.
, and
Bevilacqua, A.
,
“
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS
”
,
IEEE Solid-State Circuits Letters
, vol. 2, pp. 107-110, 2019.
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2017
D. Vogrig
,
Bevilacqua, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
A Symbol-Duty-Cycled 440-pJ/b Impulse Radio Receiver With 0.57-aJ Sensitivity in 130-nm CMOS
”
,
IEEE Transactions on Microwave Theory and Techniques
, vol. 65, pp. 565-573, 2017.
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2015
M. Caruso
,
Bassi, M.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 62, pp. 413-422, 2015.
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2013
M. Bassi
,
Caruso, M.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer
”
,
IEEE Journal of Solid-State Circuits
, vol. 48, pp. 1741-1750, 2013.
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2010
A. Bevilacqua
,
Lorenzon, L.
,
Da Dalt, N.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS
”
, in
Proceedings of the ESSCIRC 2010
, 2010, pp. 150 -153.
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2009
S. Dal Toso
,
Bevilacqua, A.
,
Tiebout, M.
,
Da Dalt, N.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS
”
, in
Proceedings of ESSCIRC 2009
, 2009, pp. 444 -447.
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2008
A. Gerosa
,
Costa, M. D.
,
Bevilacqua, A.
,
Vogrig, D.
, and
Neviani, A.
,
“
An energy-detector for non-coherent impulse-radio UWB receivers
”
, in
IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008
, 2008, pp. 2705 -2708.
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2007
A. Vallese
,
Bevilacqua, A.
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS
”
, in
Proc. of IEEE 2007 European Solid State Circuits Conference
, 2007, pp. 139 -142.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
More...