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Integrated Circuits for Analog and RF µ-Systems
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power consumption
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2007
A. Bevilacqua
,
Maniero, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
An Integrated Solution for Suppressing WLAN Signals in UWB Receivers
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 54, pp. 1617 -1625, 2007.
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2006
A. Bevilacqua
,
Pavan, F. P.
,
Sandner, C.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO
”
, in
Proceedings of the 32nd European Solid-State Circuits Conference
, 2006, pp. 440 -443.
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A. Gerosa
,
Bevilacqua, A.
,
Neviani, A.
, and
Xotta, A.
,
“
An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter
”
, in
Proceedings of 2006 IEEE International Symposium on Circuits and Systems
, 2006, p. 4 pp.
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2001
A. Gerosa
,
Neviani, A.
,
Xotta, A.
, and
Mian, G. A.
,
“
A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization
”
, in
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
, 2001, vol. 2, pp. 1099 -1102 vol.2.
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1999
A. Gerosa
and
Mian, G. A.
,
“
A low complexity EPR-IV equalizer for hard disk read channels
”
, in
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
, 1999, vol. 2, pp. 1069 -1072 vol.2.
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Recent Publications
A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS
A Reconfigurable Switched Capacitor DC–DC Converter With 1.9–6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects
Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters
More...