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Integrated Circuits for Analog and RF µ-Systems
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phase locked loops
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2024
A. Iesurum
,
Manente, D.
,
Padovan, F.
,
Bassi, M.
, and
Bevilacqua, A.
,
“
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
”
,
IEEE Journal of Solid-State Circuits
, vol. 59, pp. 294-306, 2024.
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2015
M. Caruso
,
Bassi, M.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 62, pp. 413-422, 2015.
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2007
A. Bevilacqua
,
Sandner, C.
,
Gerosa, A.
, and
Neviani, A.
,
“
Quadrature VCOs Based on Coupled PLLs
”
, in
IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007
, 2007, pp. 2140 -2143.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
More...