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Integrated Circuits for Analog and RF µ-Systems
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C
A. Celin
and
Gerosa, A.
,
“
A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior
”
, in
2016 IEEE International Symposium on Circuits and Systems (ISCAS)
, 2016, pp. 702-705.
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G
A. Gatti
,
Spiazzi, G.
,
Gerosa, A.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications
”
,
IEEE Solid-State Circuits Letters
, vol. 2, pp. 211-214, 2019.
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M
S. Marconi
,
Spiazzi, G.
,
Bevilacqua, A.
, and
Galvano, M.
,
“
A Novel Integrated Step-Up Hybrid Converter With Wide Conversion Ratio
”
,
IEEE Transactions on Power Electronics
, vol. 35, pp. 2764-2775, 2020.
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S
G. Spiazzi
,
Marconi, S.
, and
Bevilacqua, A.
,
“
Step-Up DC-DC converters combining basic topologies with charge pump
”
, in
2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL)
, 2016, pp. 1-6.
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Recent Publications
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A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
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