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Integrated Circuits for Analog and RF µ-Systems
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A. Bevilacqua
,
Vallese, A.
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers
”
, in
Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference
, 2007, pp. 420 -612.
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D. Vogrig
,
Gerosa, A.
,
Neviani, A.
,
Amat, A. G.
,
Montorsi, G.
, and
Benedetto, S.
,
“
A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code
”
,
Solid-State Circuits, IEEE Journal of
, vol. 40, pp. 753 - 762, 2005.
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D. Vogrig
,
Gerosa, A.
,
Neviani, A.
,
Graell i Amat, A.
,
Montorsi, G.
, and
Benedetto, S.
,
“
A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code
”
, in
Research in Microelectronics and Electronics, 2005 PhD
, 2005, vol. 1, pp. 31 - 34 vol.1.
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2
A. Gerosa
,
Cortelazzo, G. M.
,
Baschirotto, A.
, and
Malavasi, E.
,
“
2D video rate SC FIR filters based on analog RAMs
”
,
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
, vol. 46, pp. 1348 -1360, 1999.
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3
M. Bassi
,
Boi, G.
,
Padovan, F.
,
Fritzin, J.
,
Di Martino, S.
,
Knauder, D.
, and
Bevilacqua, A.
,
“
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS
”
,
IEEE Solid-State Circuits Letters
, vol. 2, pp. 107-110, 2019.
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4
J. Zhao
,
Bassi, M.
,
Bevilacqua, A.
,
Ghilioni, A.
,
Mazzanti, A.
, and
Svelto, F.
,
“
A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP
”
, in
European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
, 2014, pp. 179-182.
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5
S. Soldà
,
Caruso, M.
,
Bevilacqua, A.
,
Gerosa, A.
,
Vogrig, D.
, and
Neviani, A.
,
“
A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request
”
, in
Proceedings of the ESSCIRC 2010
, 2010, pp. 498 -501.
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A
A. Xotta
,
Vogrig, D.
,
Gerosa, A.
,
Neviani, A.
,
Graell i Amat, A.
,
Montorsi, G.
,
Bruccoleri, M.
, and
Betti, G.
,
“
An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels
”
, in
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
, 2002, vol. 5, p. V-69 - V-72 vol.5.
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A. Gerosa
,
Novo, A.
, and
Neviani, A.
,
“
An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process
”
, in
Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on
, 2001, pp. 152 -157.
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A. Vallese
,
Bevilacqua, A.
,
Sandner, C.
,
Tiebout, M.
,
Gerosa, A.
, and
Neviani, A.
,
“
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS
”
, in
Proc. of IEEE 2007 European Solid State Circuits Conference
, 2007, pp. 139 -142.
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A. G. I. Amatt
,
Benedetto, S.
,
Montorsi, G.
,
Vogrig, D.
,
Neviani, A.
, and
Gerosa, A.
,
“
An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code
”
, in
Communications, 2005. ICC 2005. 2005 IEEE International Conference on
, 2005, vol. 1, pp. 663 - 667 Vol. 1.
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A. Graell i Amat
,
Montorsi, G.
,
Benedetto, S.
,
Vogrig, D.
,
Neviani, A.
, and
Gerosa, A.
,
“
An analog turbo decoder for the UMTS standard
”
, in
Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on
, 2004, p. 296.
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A. Passamani
,
Ponton, D.
,
Knoblinger, G.
, and
Bevilacqua, A.
,
“
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs
”
, in
Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015
, 2015, pp. 1-4.
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C
A. Xotta
,
Gerosa, A.
, and
Neviani, A.
,
“
CMOS implementation of all-analogue APP decoders: analysis of performances and limitations
”
,
Electronics Letters
, vol. 37, pp. 1501 -1503, 2001.
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D
A. Graell i Amat
,
Benedetto, S.
,
Montorsi, G.
,
Vogrig, D.
,
Neviani, A.
, and
Gerosa, A.
,
“
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code
”
,
Communications, IEEE Transactions on
, vol. 54, pp. 1973 -1982, 2006.
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L
A. Passamani
,
Ponton, D.
,
Knoblinger, G.
, and
Bevilacqua, A.
,
“
A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers
”
, in
2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
, 2014, pp. 1-4.
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A. Maniero
,
Bevilacqua, A.
,
Gerosa, A.
, and
Neviani, A.
,
“
A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency
”
, in
13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06.
, 2006, pp. 90 -93.
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M
A. Gerosa
,
Novo, A.
,
Mengalli, A.
, and
Neviani, A.
,
“
A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker
”
, in
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
, 2001, vol. 1, pp. 296 -299 vol. 1.
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P
A. Gerosa
,
Neviani, A.
, and
Cortelazzo, G. M.
,
“
A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters
”
, in
Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on
, 1999, pp. 195 -198.
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A. Novo
,
Gerosa, A.
,
Neviani, A.
,
Mozzi, A.
, and
Zanoni, E.
,
“
Programmable voltage multiplier for pacemaker output pulse generation
”
,
Electronics Letters
, vol. 35, pp. 560 -561, 1999.
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U
A. Bevilacqua
and
Niknejad, A. M.
,
“
An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers
”
, in
Digest of Technical Papers of 2004 IEEE International Solid-State Circuits Conference
, 2004, pp. 382 - 533 Vol.1.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
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A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
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