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Integrated Circuits for Analog and RF µ-Systems
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M. Bassi
,
Zhao, J.
,
Bevilacqua, A.
,
Ghilioni, A.
,
Mazzanti, A.
, and
Svelto, F.
,
“
A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP
”
,
IEEE Journal of Solid-State Circuits
, vol. 50, pp. 1618-1628, 2015.
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P
F. Padovan
,
Tiebout, M.
,
Mertens, K. L. R.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 62, pp. 607-615, 2015.
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A. Passamani
,
Ponton, D.
,
Knoblinger, G.
, and
Bevilacqua, A.
,
“
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs
”
, in
Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015
, 2015, pp. 1-4.
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S
P. Scaramuzza
,
Rubino, C.
,
Caruso, M.
,
Tiebout, M.
,
Bevilacqua, A.
, and
Neviani, A.
,
“
Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 65, no. 11, pp. 3780 - 3789, 2018.
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T
L. Tomasin
,
Iesurum, A.
,
Gobbo, A.
,
Neviani, A.
, and
Bevilacqua, A.
,
“
A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies
”
,
IEEE Transactions on Circuits and Systems II: Express Briefs
, pp. 1-1, 2024.
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Recent Publications
Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters
A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies
More...