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Filters: Author is Dartizio, Simone M.  [Clear All Filters]
2022
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
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S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time”, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.
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ICARUS - Integrated Circuits for Analog and RF µ-Systems

Dipartimento di Ingegneria dell’Informazione , Via Gradenigo 6/B, 35131 Padova, Italy

University of Padova

Phone: +39 049 827 7794

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Recent Publications

  • A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
  • GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse
  • Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices
  • A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
  • A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time
More...