D.  Frassetto, Cabizza, S., Zilio, N. ', Karim, A., Garbossa, C., Agostinelli, M., Spiazzi, G., Bevilacqua, A., and Neviani, A., ?A Highly Integrated Dual-Path Step-Down Hybrid DC?DC Converter With Self-Balanced Flying Capacitor and Reduced Inductor Current?, IEEE Open Journal of Power Electronics, vol. 7, pp. 167-179, 2026.

A.  Bevilacqua and Mazzanti, A., ?On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, pp. 1777-1786, 2026.

L.  Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., ?A 0.13-?m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication?, IEEE Journal of Solid-State Circuits, pp. 1-12, 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS?, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.

D.  Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., ?A 5.1?10.5 GHz SiGe BiCMOS Power Amplifier for 6GNR with 29 dBm PSAT and 40.1% PAE?, in 2025 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2025.

D.  Pecile, Pollin, A., Dal Maistro, D., Gambarucci, A., De Astis, G., and Bevilacqua, A., ?A 5-7 GHz BiCMOS Front-End Module for WiFi 6e with 2.2 dB NF and 16 dBm PAVG at ?40 dB EVM?, in 2025 20th European Microwave Integrated Circuits Conference (EuMIC), 2025.

L.  Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., ?A 5.75mW Fully-Integrated Galvanic Isolator for Gate Drivers with Asynchronous 66.7/66.7 Mb/s Full-Duplex Communication?, in 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2025.

D.  Frassetto, Cabizza, S., Karim, A., Spiazzi, G., Bevilacqua, A., and Neviani, A., ?Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter?, in 2025 IEEE Nordic Circuits and Systems Conference (NorCAS), 2025.

D.  Pecile, Gambarucci, A., Kokorovic, S., and Bevilacqua, A., ?Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm P SAT and 40.1% PAE?, IEEE Transactions on Microwave Theory and Techniques, pp. 1-12, 2025.

L.  Guglielmini and Bevilacqua, A., ?Analysis of a gm-C Complex Filter for Low Power Wireless Receivers?, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications?, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

D.  Frassetto, Cabizza, S., Agostinelli, M., Garbossa, C., Spiazzi, G., Bevilacqua, A., and Neviani, A., ?Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters?, in 2025 International Conference on IC Design and Technology (ICICDT), 2025.

L.  Navarin, Neviani, A., and Bevilacqua, A., ?A DLL-Based FSK Demodulator for Asynchronous Communications?, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

L.  Bellemo, Neviani, A., and Bevilacqua, A., ?A Driving Methodology for Four-Quadrant Power Switches Using CMOS Transistor Stacking?, in 2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS), 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers?, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9, 2025.

L.  Navarin, Norling, K., Parenzan, M., Ruzzu, S., Neviani, A., and Bevilacqua, A., ?A Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication?, IEEE Solid-State Circuits Letters, vol. 8, pp. 289-292, 2025.

D.  Pecile, Gambarrucci, A., Kokorovic, S., and Bevilacqua, A., ?A Study of the Efficiency of Output-Matched Radiofrequency Power Amplifiers?, Analog Integrated Circuits and Signal Processing, vol. 125, no. 3, p. 42, 2025.

L.  Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., ?A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1?s?, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

A.  Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., ?Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs?, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

L.  Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., ?Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters?, IEEE Transactions on Microwave Theory and Techniques, vol. 72, pp. 2840-2851, 2024.

N.  Zugno and Bevilacqua, A., ?Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology?, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

A.  Bevilacqua and Mazzanti, A., ?Analysis of CMRR in Doubly-Tuned Transformer Baluns?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4874-4878, 2024.

L.  Bellemo and Bevilacqua, A., ?On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 3715-3719, 2024.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers?, in 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024.

D.  Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., ?On the Efficiency of Output-Matched Radiofrequency Power Amplifiers?, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

L.  Bellemo, Spiazzi, G., and Bevilacqua, A., ?On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting?, in 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024.

L.  Tomasin, Iesurum, A., Gobbo, A., Neviani, A., and Bevilacqua, A., ?A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4718-4722, 2024.

F.  Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., ?A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner?, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

D.  Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 607-617, 2023.

N.  Zugno, Brandonisio, F., Niederfriniger, T., and Bevilacqua, A., ?On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies?, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

L.  Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., ?A Reactive Passive Mixer for 16-QAM Cartesian IoT Transmitters in 22 nm FD-SOI CMOS?, in 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2023.

L.  Tomasin and Bevilacqua, A., ?A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem?, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

L.  Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., ?A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise?, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.

A.  Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS?, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., ?A 68.6fs_rms-Total-integrated-Jitter and 1.5?s-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching?, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

F.  Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., ?A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler?, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

A.  Bettini, Cosnier, T., Magnani, A., Syshchyk, O., Borga, M., Decoutere, S., and Neviani, A., ?Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology?, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022.

F.  Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications?, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

N.  Modolo, De Santi, C., Baratella, G., Bettini, A., Borga, M., Posthuma, N., Bakeroot, B., You, S., Decoutere, S., Bevilacqua, A., Neviani, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., ?Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices?, IEEE Transactions on Electron Devices, pp. 1-6, 2022.

S. M.  Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., ?A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 ? s-Locking-Time?, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.

C.  Shi, Song, M., Gao, Z., Bevilacqua, A., Dolmans, G., and Liu, Y. - H., ?Galvanic-Coupled Trans-Dural Data Transfer for High-Bandwidth Intracortical Neural Sensing?, IEEE Transactions on Microwave Theory and Techniques, vol. 70, pp. 4579-4589, 2022.

F.  Chiocchetta, De Santi, C., Rampazzo, F., Mukherjee, K., Grünenpütt, J., Sommer, D., Blanck, H., Lambert, B., Gerosa, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., ?GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse?, in 2022 IEEE International Reliability Physics Symposium (IRPS), 2022.

L.  Tomasin, Boi, G., Padovan, F., and Bevilacqua, A., ?A 10.7?14.1 GHz Reconfigurable Octacore DCO with ?126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS?, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.

A.  Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS?, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.

D.  Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A 22?31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS?, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

A.  Bevilacqua and Mazzanti, A., ?Doubly-Tuned Transformer Networks: A Tutorial?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, pp. 550-555, 2021.

S.  Veni, Caruso, M., Seebacher, D., Neviani, A., and Bevilacqua, A., ?A Fully Integrated 28 GHz Class-J Doherty Power Amplifier in 130 nm BiCMOS?, in SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, 2021.

P.  Andreani and Bevilacqua, A., ?Harmonic Oscillators in CMOS?A Tutorial Overview?, IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 2-17, 2021.

A.  Bilato, Issakov, V., Mazzanti, A., and Bevilacqua, A., ?A Multichannel D-Band Radar Receiver With Optimized LO Distribution?, IEEE Solid-State Circuits Letters, vol. 4, pp. 141-144, 2021.

G.  Marin, Kim, J., Seo, J. - M., and Neviani, A., ?A 13.56 MHz Reconfigurable Step-Up Switched Capacitor Converter for Wireless Power Transfer System in Implantable Medical Devices?, in 2020 IEEE Wireless Power Transfer Conference (WPTC), 2020.

A.  Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects?, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.

D.  Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., ?A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS?, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.

S.  Veni, Andreani, P., Caruso, M., Tiebout, M., and Bevilacqua, A., ?Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO?, IEEE Journal of Solid-State Circuits, vol. 55, pp. 2345-2355, 2020.

A.  Bevilacqua, ?Fundamentals of Integrated Transformers: From Principles to Applications?, IEEE Solid-State Circuits Magazine, vol. 12, pp. 86-100, 2020.

S.  Marconi, Spiazzi, G., Bevilacqua, A., and Galvano, M., ?A Novel Integrated Step-Up Hybrid Converter With Wide Conversion Ratio?, IEEE Transactions on Power Electronics, vol. 35, pp. 2764-2775, 2020.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters?, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?A Reconfigurable Switched Capacitor DC?DC Converter With 1.9?6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS?, IEEE Solid-State Circuits Letters, vol. 3, pp. 106-109, 2020.

A.  Bilato, Issakov, V., and Bevilacqua, A., ?A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 ?m SiGe BiCMOS?, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

A.  Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., ?A 130-nm CMOS Dual Input-Polarity DC?DC Converter for Low-Power Applications?, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.

S.  Veni, Caruso, M., Tiebout, M., and Bevilacqua, A., ?A 17 GHz All-npn Push-Pull Class-C VCO?, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

F.  Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications?, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.

A.  Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., ?A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion?, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.

M.  Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., ?A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS?, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.

A.  Bilato, Issakov, V., and Bevilacqua, A., ?Considerations on 120GHz LO Signal Generation and Distribution for Highly-Integrated Multi-Channel Radar Transceivers?, in 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019.

M.  Ruzzarin, Meneghini, M., de Santi, C., Neviani, A., Yu, F., Strempel, K., Fatahilah, M. Fahlesa, Witzigmann, B., Wasisto, H. Suryo, Waag, A., Meneghesso, G., and Zanoni, E., ?Demonstration of UV-Induced Threshold Voltage Instabilities in Vertical GaN Nanowire Array-Based Transistors?, IEEE Transactions on Electron Devices, vol. 66, pp. 2119-2124, 2019.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters?, in 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019.

A.  Gerosa, Bevilacqua, A., and Spiazzi, G., ?A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology?, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

G.  Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., ?Non-isolated High Step-up DC-DC Converter with Minimum Switch Voltage Stress?, IEEE Transactions on Power Electronics, vol. 34, no. 2, pp. 1470-1480, 2019.

D.  Oloumi, Bevilacqua, A., and Bassi, M., ?UWB Radar for High Resolution Breast Cancer Scanning: System, Architectures, and Challenges?, in 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019.

A.  Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., ?A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner?, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.

P.  Scaramuzza, Rubino, C., Caruso, M., Tiebout, M., Bevilacqua, A., and Neviani, A., ?Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3780 - 3789, 2018.

S.  Marconi, Barbero, M. B., Fougeron, D., Godiot, S., Menouni, M., Pangaud, P., Rozanov, A., Breugnon, P., Bomben, M., Calderini, G., Crescioli, F., Le Dortz, O., Marchiori, G., Dzahini, D., Rarbi, F. E., Gaglione, R., Krüger, H., Daas, M., Dieter, Y., Hemperek, T., Hügging, F., Moustakas, K., Pohl, D., Rymaszewski, P., Standke, M., Vogt, M., Wang, T., Wermes, N., Karagounis, M., Stiller, A., Marzocca, C., Marzocca, G., De Robertis, G., Loddo, F., Licciulli, F., Andreazza, A., Liberali, V., Stabile, A., Frontini, L., Bagatin, M., Bisello, D., Gerardin, S., Mattiazzo, S., Paccagnella, A., Vogrig, D., Bonaldo, S., Bacchetta, N., Gaioni, L., De Canio, F., Manghisoni, M., Re, V., Riceputi, E., Traversi, G., Ratti, L., Vacchi, C., Androsov, K., Beccherle, R., Magazzu, G., Minuti, M., Morsani, F., Palla, F., Poulios, S., Bilei, G. M., Menichelli, M., Placidi, P., Dellacasa, G., Demaria, N., Mazza, G., Monteil, E., Pacher, L., Paternò, A., Rivetti, A., Rolo, M. D. Da Roch, Gajanana, D., Gromov, V., van Eijk, B., Kluit, R., Vitkovskiy, A., Benka, T., Havranek, M., Janoska, Z., Marcisovsky, M., Neue, G., Tomasek, L., Kafka, V., Vrba, V., Lopez-Morillo, E., Palomo, F. R., Muñoz, F., Vila, I., Jiménez, E. M. S., Abbaneo, D., Christiansen, J., Orfanelli, S., Casas, L. M. Jara, Conti, E., Bell, S., Prydderch, M. L., Thomas, S., Christian, D. C., Deptuch, G., Fahim, F., Hoff, J., Lipton, R., Liu, T., Zimmerman, T., Miryala, S., Garcia-Sciveres, M., Gnani, D., Krieger, A., Papadopoulou, K., Heim, T., Carney, R., Nachman, B., Renteira, C., Wallangen, V., Hoeferkamp, M., and Seidel, S., ?Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC?, in 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018.

A.  Franceschin, Padovan, F., Nonis, R., and Bevilacqua, A., ?On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 657 - 661, 2018.

F.  Padovan, Quadrelli, F., Bassi, M., Tiebout, M., and Bevilacqua, A., ?A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations?, in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.

F.  Pepe, Bevilacqua, A., and Andreani, P., ?On the Remarkable Performance of the Series-Resonance CMOS Oscillator?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 531-542, 2018.

A.  Mazzanti and Bevilacqua, A., ?Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4157 - 4168, 2018.

A.  Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., ?A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE?, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.

F.  Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset?, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.

P.  Scaramuzza, Rubino, C., Tiebout, M., Caruso, M., Ortner, M., Neviani, A., and Bevilacqua, A., ?Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems?, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 187-190.

G.  Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., ?Non-isolated high step-up DC-DC converter with minimum switch voltage stress?, in 2017 IEEE Southern Power Electronics Conference (SPEC), 2017.

D.  Vogrig, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A Symbol-Duty-Cycled 440-pJ/b Impulse Radio Receiver With 0.57-aJ Sensitivity in 130-nm CMOS?, IEEE Transactions on Microwave Theory and Techniques, vol. 65, pp. 565-573, 2017.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation?, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers?, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.

S.  Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., ?A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.

A.  Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., ?Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers?, Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 307-315, 2016.

A.  Celin and Gerosa, A., ?A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior?, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.

G.  Spiazzi, Marconi, S., and Bevilacqua, A., ?Step-Up DC-DC converters combining basic topologies with charge pump?, in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1-6.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation?, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.

M.  Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., ?A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 413-422, 2015.

M.  Bassi, Zhao, J., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., ?A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP?, IEEE Journal of Solid-State Circuits, vol. 50, pp. 1618-1628, 2015.

A.  Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., ?Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs?, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015, 2015, pp. 1-4.

A.  Bevilacqua, ?CMOS UWB Transceivers for Short-Range Microwave Medical Imaging?, in Wireless transceiver circuits, Boca Raton: CRC Press, Taylor & Francis group, 2015, pp. 305?333.

F.  Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., ?Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.

A.  Celin and Gerosa, A., ?Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ?? ADCs?, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1454-1457.

A.  Mazzanti and Bevilacqua, A., ?On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 2334-2341, 2015.

F.  Padovan, Tiebout, M., Dielacher, F., Bevilacqua, A., and Neviani, A., ?SiGe BiCMOS VCO with 27% tuning range for 5G communications?, in 2015 Asia-Pacific Microwave Conference (APMC), 2015, vol. 1, pp. 1-3.

D.  Vogrig, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A symbol-duty-cycled 440 pJ/b impulse radio receiver with 0.57 aJ sensitivity in 130 nm CMOS?, in Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE, 2015, pp. 243-246.

F.  Padovan, Bevilacqua, A., and Neviani, A., ?A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS?, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 287-290.

A. D.  Capobianco, Khan, M. S., Caruso, M., and Bevilacqua, A., ?3-18 GHz compact planar antenna for short-range radar imaging?, Electronics Letters, vol. 50, pp. 1016-1018, 2014.

J.  Zhao, Bassi, M., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., ?A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP?, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 179-182.

A.  Bevilacqua and Neviani, A., ?Energy-efficient ultra-wideband impulse radios for short-range low-data rate communications?, in 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014, pp. 874-877.

A.  Bevilacqua, ?Great lessons from the back of the envelope?, IEEE Solid-State Circuits Magazine, vol. 6, pp. 45-45, 2014.

A.  Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., ?A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers?, in 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2014, pp. 1-4.

M.  Caruso, Bevilacqua, A., and Neviani, A., ?An X-Band Lumped-Element Wilkinson Combiner With Embedded Impedance Transformation?, IEEE Microwave and Wireless Components Letters, vol. 24, pp. 689-691, 2014.

M.  Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., ?A 2-16GHz 204mW 3mm-Resolution Stepped Frequency Radar for Breast Cancer Diagnostic Imaging in 65nm CMOS?, in IEEE ISSCC Digest of Technical Papers, 2013, pp. 204-241.

M.  Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., ?A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer?, IEEE Journal of Solid-State Circuits, vol. 48, pp. 1741-1750, 2013.

M.  Bassi, Caruso, M., Khan, M. S., Bevilacqua, A., Capobianco, A. - D., and Neviani, A., ?An Integrated Microwave Imaging Radar With Planar Antennas for Breast Cancer Detection?, IEEE Transactions on Microwave Theory and Techniques, vol. 61, pp. 2108-2118, 2013.

F.  Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., ?A K-band SiGe bipolar VCO with transformer-coupled varactor for backhaul links?, in 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF),, 2013, pp. 108-110.

M.  Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., ?Wideband {2?16GHz} local oscillator generation for short-range radar applications?, in Proceedings of the 2013 ESSCIRC, 2013, pp. 49-52.

M.  Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., ?A 1.75?15 GHz Stepped Frequency Receiver for Breast Cancer Imaging in 65nm CMOS?, in Proc. of the IEEE European Solid-State Circuits Conference, 2012, pp. 353?356.

A.  Bevilacqua and Andreani, P., ?A 2.7?6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2?, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, pp. 1?10, 2012.

A.  Bevilacqua and Andreani, P., ?An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators?, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, pp. 938 -945, 2012.

M.  Bassi, Bevilacqua, A., Gerosa, A., and Neviani, A., ?Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints?, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, pp. 1228 -1241, 2012.

A.  Gerosa, Bevilacqua, A., and Neviani, A., ?A local oscillator for WCDMA band VII based on frequency multiplication?, Analog Integrated Circuits and Signal Processing, vol. 72, no. 1, 2012.

A.  Neviani, Bevilacqua, A., Gerosa, A., and Vogrig, D., ?Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications?, in  2012 IEEE International Conference on IC Design Technology (ICICDT), 2012, pp. 1 -4.

A.  Bevilacqua and Andreani, P., ?Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, pp. 20 -24, 2012.

F.  Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., ?A SiGe bipolar VCO for backhaul E-band communication systems?, in Proceedings of the 2012 ESSCIRC, 2012, pp. 402 -405.

M.  Camponeschi, Bevilacqua, A., Tiebout, M., and Neviani, A., ?A X-Band I/Q Upconverter in 65 nm CMOS for High Resolution FMCW Radars?, IEEE Microwave and Wireless Components Letters, vol. 22, pp. 141 -143, 2012.

A.  Bevilacqua and Andreani, P., ?A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2?, in NORCHIP, 2011, 2011, pp. 1 -4.

S.  Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., ?A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13um CMOS?, IEEE Journal of Solid-State Circuits, vol. 46, pp. 1636 -1647, 2011.

A.  Bevilacqua and Andreani, P., ?On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory?, in 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 2011, pp. 217 -220.

M.  Bassi, Bevilacqua, A., Gerosa, A., and Neviani, A., ?Integrated Transceivers for UWB Breast Cancer Imaging: Architecture and Circuit Constraints?, in 2011 IEEE International Symposium on Circuits and Systems, 2011, pp. 2087-2090.

C.  Fantozzi, Vangelista, L., Vogrig, D., and Campana, O., ?SDR implementation of a DVB-T2 transmitter: The core building blocks?, in 2011 IEEE International Conference on Consumer Electronics (ICCE), 2011, pp. 391 -392.

M.  Camponeschi, Bevilacqua, A., and Andreani, P., ?Time-variant analysis and design of a power efficient ISM-band quadrature receiver?, Analog Integrated Circuits and Signal Processing, vol. 67, pp. 11-20, 2011.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS?, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.

A.  Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., ?A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS?, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.

S.  Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., ?A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request?, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.

M.  Camponeschi, Bevilacqua, A., Neviani, A., and Andreani, P., ?Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end?, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2063 -2066.

A.  Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., ?A digitally programmable ring oscillator in the UWB range?, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),, 2010, pp. 1101 -1104.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands S Through Ku?, IEEE Transactions on Microwave Theory and Techniques, vol. 58, pp. 1686 -1695, 2010.

S.  Soldà, Caruso, M., Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., ?Low-power UWB transmitter using a combined mixer and power amplifier?, in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 333 -336.

S.  Dal Toso, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks?, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 1903 -1906.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS?, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.

M.  Camponeschi, Bevilacqua, A., and Andreani, P., ?Analysis and design of a low-power single-stage CMOS wireless receiver?, in Proc. of 2009 NORCHIP, 2009, pp. 1 -4.

A.  Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems?, IEEE Journal of Solid-State Circuits, vol. 44, pp. 331 -343, 2009.

A.  Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., ?An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 1030 -1040, 2009.

A.  Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS?, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.

S.  Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., ?Analog decoding of trellis coded modulation for multi-level flash memories?, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.

J.  Borremans, Bevilacqua, A., Bronckers, S., Dehan, M., Kuijk, M., Wambacq, P., and Craninckx, J., ?A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS?, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2693 -2705, 2008.

A.  Bevilacqua, Camponeschi, M., Tiebout, M., Gerosa, A., and Neviani, A., ?Design of broadband inductorless LNAs in ultra-scaled CMOS technologies?, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008. , 2008, pp. 1300 -1303.

A.  Gerosa, Costa, M. D., Bevilacqua, A., Vogrig, D., and Neviani, A., ?An energy-detector for non-coherent impulse-radio UWB receivers?, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008, 2008, pp. 2705 -2708.

S. D.  Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, in Digest of Technical Papers of 2008 IEEE International Solid-State Circuits Conference, 2008, pp. 124 -601.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2844 -2852, 2008.

A.  Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers?, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.

A.  Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., ?A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver?, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.

A.  Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS?, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.

A.  Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., ?An Integrated Solution for Suppressing WLAN Signals in UWB Receivers?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, pp. 1617 -1625, 2007.

A.  Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., ?Quadrature VCOs Based on Coupled PLLs?, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 2140 -2143.

A.  Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., ?Transformer-Based Dual-Mode Voltage-Controlled Oscillators?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, pp. 293 -297, 2007.

A.  Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., ?A 0.35 um SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection?, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 1015 -1018.

A.  Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., ?A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO?, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

A.  Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., ?An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling ? ? Modulator and a Flash Converter?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.

A.  Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., Neviani, A., and Gerosa, A., ?CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code?, in Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE, 2006, pp. 1 -6.

A.  Graell i Amat, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., ?Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code?, Communications, IEEE Transactions on, vol. 54, pp. 1973 -1982, 2006.

A.  Gerosa, Elettronica Digitale, Esercizi risolti. PADOVA: Edizioni Libreria Progetto, 2006, pp. 1?216.

A.  Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., ?A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers?, IEEE Microwave and Wireless Components Letters, vol. 16, pp. 134 -136, 2006.

A.  Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., SOLDA, S., Neviani, A., and Gerosa, A., ?Iterative Analog Decoder for a SCCC?, in Analog Decoding Workshop, 2006.

A.  Maniero, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency?, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 90 -93.

A.  Gerosa, Bevilacqua, A., Neviani, A., and Xotta, A., ?An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter?, in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, 2006, p. 4 pp.

D.  Vogrig, Gerosa, A., Neviani, A., Amat, A. G., Montorsi, G., and Benedetto, S., ?A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code?, Solid-State Circuits, IEEE Journal of, vol. 40, pp. 753 - 762, 2005.

D.  Vogrig, Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., and Benedetto, S., ?A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code?, in Research in Microelectronics and Electronics, 2005 PhD, 2005, vol. 1, pp. 31 - 34 vol.1.

A.  Gerosa and Neviani, A., ?A 1.8uW Sigma-Delta Modulator for 8-bit Digitization of Cardiac Signals in Implantable Pacemakers Operating Down to 1.8V?, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, vol. 52, pp. 71?76, 2005.

A. G. I.  Amatt, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., ?An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code?, in Communications, 2005. ICC 2005. 2005 IEEE International Conference on, 2005, vol. 1, pp. 663 - 667 Vol. 1.

A.  Xotta, Gerosa, A., and Neviani, A., ?A Multi-Mode Sigma-Delta Analog-to-Digital Converter for GSM, UMTS and WLAN?, in ISCAS, 2005.

A.  Bevilacqua and Svelto, F., ?Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, pp. 117 - 121, 2005.

A.  Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., ?An analog turbo decoder for the UMTS standard?, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.

A.  Gerosa, Elettronica Digitale, Esercizi Risolti. PADOVA ? ITA: Libreria Progetto, 2004, pp. 1?161.

A.  Gerosa, Maniero, A., and Neviani, A., ?A Fully-Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemakers?, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 51, pp. 1916?1925, 2004.

A.  Gerosa, Neviani, A., and Maniero, A., ?A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers?, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, pp. 1083?1093, 2004.

A.  Gerosa and Neviani, A., ?A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER?, in ISCAS, 2004, vol. 2, pp. 245?248.

A.  Xotta, Gerosa, A., and Neviani, A., ?A Programmable-Order Sigma-Delta Converter for a Multi-Standard Wireless Receiver?, in WowCas, Vancouver B.C., Canada, 2004, vol. 1, pp. 33?34.

A.  Bevilacqua and Niknejad, A. M., ?An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers?, in Digest of Technical Papers of 2004 IEEE International Solid-State Circuits Conference, 2004, pp. 382 - 533 Vol.1.

A.  Bevilacqua and Niknejad, A.  M., ?An Ultrawideband CMOS Low-Noise Amplifier for 3.1?10.6-GHz Wireless Receivers?, IEEE Journal of Solid-State Circuits, vol. 39, pp. 2259?2268, 2004.

M.  PERENZONI, Gerosa, A., and Neviani, A., ?Analog CMOS Implementation of Gallager?s Interative Decoding algorithm applied to a Block Turbo Code?, in ISCAS, 2003, vol. 5, pp. 813?816.

A.  Gerosa and Neviani, A., ?Enhancing Output Voltage Swing in Low-Voltage Micro-Power OTA Using Self-Cascode?, ELECTRONICS LETTERS, vol. 39, pp. 638?639, 2003.

A.  Gerosa, Xotta, A., Neviani, A., and Mian, G. A., ?Frequency Offset Compensation in Fractionally Spaced Equalization?, IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS, vol. 150, pp. 134?140, 2003.

A.  Gerosa, Maniero, A., and Neviani, A., ?A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers?, in ESSCIRC, 2003, vol. 1, pp. 157?160.

A.  Maniero, Gerosa, A., and Neviani, A., ?Performance Optimization in Micro-Power, Low-Voltage, Log-Domain Filters in Pure CMOS Technology?, in ISCAS, 2003, vol. 1, pp. 565?568.

A.  Gerosa and Neviani, A., ?A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V?, in ISCAS, 2003, vol. 5, pp. 49?52.

A.  Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., ?An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels?, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.

A.  Gerosa, Bernardini, R., and Pietri, S., ?A Fully Integrated Chaotic System for the Generation of Truly Random Numbers?, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, vol. 49, pp. 993?1000, 2002.

A.  Bevilacqua and Svelto, F., ?Non-linear spectral analysis of direct conversion wireless receivers?, in IEEE 2002 Radio and Wireless Conference, 2002, pp. 39 - 42.

A.  Gerosa, Novo, A., and Neviani, A., ?An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process?, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.

A.  Xotta, Gerosa, A., and Neviani, A., ?CMOS implementation of all-analogue APP decoders: analysis of performances and limitations?, Electronics Letters, vol. 37, pp. 1501 -1503, 2001.

A.  Gerosa, ?Design of Power-Optimized OTAs for SC Applications?. 2001.

A.  Gerosa, Bernardini, R., and Pietri, S., ?A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system?, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 87 -92.

A.  Gerosa, Novo, A., Mengalli, A., and Neviani, A., ?A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker?, in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001, vol. 1, pp. 296 -299 vol. 1.

A.  Gerosa, Neviani, A., Xotta, A., and Mian, G. A., ?A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization?, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 1099 -1102 vol.2.

A.  Gerosa, ?A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption?, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 949 -952 vol.2.

A.  Gerosa, RUBIN, R., and Neviani, A., ?A Simplified Analysis of Noise in Switched Capacitor Networks from a Circuit Design Perspective?, in ECCTD, 2001, vol. 1, pp. 261?264.

A.  Novo, Gerosa, A., and Neviani, A., ?A Sub-Micron CMOS Programmable Charge Pump for Implantable Pacemaker?, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol. 27, pp. 211?217, 2001.

A.  Novo, Gerosa, A., Neviani, A., Mozzi, A., and Zanoni, E., ?A CMOS 0.8 um programmable charge pump for the output stage of an implantable pacemaker?, in Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on, 2000, pp. 34/1 -34/5.

A.  Gerosa, Novo, A., and Neviani, A., ?Low-power sensing and digitization of cardiac signals based on sigma-delta conversion?, in Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on, 2000, pp. 216 - 218.

A.  Gerosa, Cortelazzo, G. M., Baschirotto, A., and Malavasi, E., ?2D video rate SC FIR filters based on analog RAMs?, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 46, pp. 1348 -1360, 1999.

A.  Gerosa and Mian, G. A., ?A low complexity EPR-IV equalizer for hard disk read channels?, in Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on, 1999, vol. 2, pp. 1069 -1072 vol.2.

A.  Gerosa, Neviani, A., and Cortelazzo, G. M., ?A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters?, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.

A.  Novo, Gerosa, A., Neviani, A., Mozzi, A., and Zanoni, E., ?Programmable voltage multiplier for pacemaker output pulse generation?, Electronics Letters, vol. 35, pp. 560 -561, 1999.

A.  Novo, Gerosa, A., Neviani, A., Zanoni, E., and Mozzi, A., ?Programmable voltage multipliers for pacemaker output pulse generation in CMOS 0.8 um technology?, in Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European, 1999, pp. 386 - 389.

A.  Gerosa, Neviani, A., and Zanoni, E., ?A SC Video Filter with Analog-RAM-based Delay Efficient Realization?, in ECCTD, 1999, vol. 2, pp. 1247?1250.

G.  MENEGHESSO, Zanoni, E., Gerosa, A., PAVAN, P., STADLER, W., ESMARK, K., and GUGGENMOS, G., ?Test structures and testing methods for electrostatic discharge: results of PROPHECY project?, MICROELECTRONICS RELIABILITY, vol. 39, pp. 635?646, 1999.

A.  Gerosa and Mian, G. A., ?An Equalizer for Hard Disk Drive Channels, with Low Sensitivity to Sampling Phase Variation?, in EUSIPCO-98, 1998, vol. 1, pp. 483?486.

G. M.  Cortelazzo, Malavasi, E., Gerosa, A., and Neviani, A., ?A New Structure for Video-Rate 2D SC FIR Filters?, in EUSIPCO-96, 1996, vol. 2, pp. 1307?1310.