@article {704,
	title = {A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41\% Peak DE in 22 nm CMOS},
	journal = {IEEE Solid-State Circuits Letters},
	volume = {8},
	year = {2025},
	pages = {217 - 220},
	chapter = {217},
	keywords = {BLE, BT, Clocks, CMOS, Computer architecture, delays, Digital Doherty PA, Impedance, Microprocessors, Modulation, multi-class PA, power amplifiers, Power generation, SCPA, transmitters, uneven Doherty, Voltage},
	doi = {10.1109/LSSC.2025.3591570},
	author = {Fietta, Edoardo Baiesi and Seebacher, David and Ponton, Davide and Bevilacqua, A.}
}
@conference {768617,
	title = {A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters},
	booktitle = {Mixed-Signal Design, 1999. SSMSD {\textquoteright}99. 1999 Southwest Symposium on},
	year = {1999},
	pages = {195 -198},
	keywords = {0.8 micron, 2D SC FIR filters, analogue storage, CMOS analogue integrated circuits, CMOS technology, convolution, delay efficient realization, delays, filter impulse response symmetry, filter phase linearity, FIR filters, inner filter delays, partial accumulation analog-RAM-based architecture, partial convolution products, picture-in-picture applications, random-access storage, switched capacitor filters, transient response, video applications, video signal processing},
	doi = {10.1109/SSMSD.1999.768617},
	author = {Gerosa, A. and Neviani, A. and Cortelazzo, G.M.}
}
