@conference {4150707,
	title = {CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code},
	booktitle = {Global Telecommunications Conference, 2006. GLOBECOM {\textquoteright}06. IEEE},
	year = {2006},
	pages = {1 -6},
	keywords = {analog iterative decoder, analog memory, block length, code rate, concatenated codes, convolutional codes, interleaved codes, iterative decoding, performance mismatch impact, reconfigurable analog decoder, reconfigurable interleaver, serially concatenated convolutional code, single-input single-output, SISO decoder, trellis code, trellis codes},
	issn = {1930-529X},
	doi = {10.1109/GLOCOM.2006.77},
	author = {Graell i Amat, A. and Vogrig, D. and Benedetto, S. and Montorsi, G. and Neviani, A. and Gerosa, A.}
}
@conference {1542996,
	title = {A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code},
	booktitle = {Research in Microelectronics and Electronics, 2005 PhD},
	volume = {1},
	year = {2005},
	pages = {31 - 34 vol.1},
	keywords = {0.35 micron, 1.36 nJ, 132 bit, 2 Mbit/s, 3G mobile communication, 3GPP standard, 40 bit, 6.6 mW, channel coding, CMOS analog turbo decoder, CMOS analogue integrated circuits, concatenated codes, parallel concatenated code, turbo codes, UMTS channel code, wireless data transmission systems},
	doi = {10.1109/RME.2005.1542996},
	author = {Vogrig, D. and Gerosa, A. and Neviani, A. and Graell i Amat, A. and Montorsi, G. and Benedetto, S.}
}
