@conference {688,
	title = {A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs},
	booktitle = {2024 IEEE European Solid-State Electronics Research Conference (ESSERC)},
	year = {2024},
	keywords = {CMOS, Digital Phase-locked loops (DPLLs), digital pre-distortion, digitally-controlled oscillator (DCO), fast locking, Frequency modulation, frequency synthesizers, Jitter, mm-Wave, Phase modulation, Power demand, Prototypes, Spread spectrum communication, Standards, Time-frequency analysis, Transient analysis, Wireless communication},
	doi = {10.1109/ESSERC62670.2024.10719534},
	author = {Grimaldi, Luigi and Iesurum, Agata and Boi, Giovanni and Versolatto, Fabio and Steffan, Giovanni and Padovan, Fabio and Koltsov, Heorhii and Bevilacqua, A. and Cherniak, Dmytro}
}
@article {4684650,
	title = {UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking},
	journal = {IEEE Journal of Solid-State Circuits},
	volume = {43},
	number = {12},
	year = {2008},
	pages = {2844 -2852},
	keywords = {CMOS integrated circuits, CMOS prototype synthesizes, current 30 mA, fast hopping carriers, frequency 8.71 GHz, frequency hop communication, frequency synthesizers, size 90 nm, sub harmonic injection locking, ultra wideband communication, UWB fast hopping frequency generation, voltage 1.2 V, WiMedia},
	issn = {0018-9200},
	doi = {10.1109/JSSC.2008.2005702},
	author = {Dal Toso, S. and Bevilacqua, A. and Tiebout, M. and Marsili, S. and Sandner, C. and Gerosa, A. and Neviani, A.}
}
