@article {704,
	title = {A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41\% Peak DE in 22 nm CMOS},
	journal = {IEEE Solid-State Circuits Letters},
	volume = {8},
	year = {2025},
	pages = {217 - 220},
	chapter = {217},
	keywords = {BLE, BT, Clocks, CMOS, Computer architecture, delays, Digital Doherty PA, Impedance, Microprocessors, Modulation, multi-class PA, power amplifiers, Power generation, SCPA, transmitters, uneven Doherty, Voltage},
	doi = {10.1109/LSSC.2025.3591570},
	author = {Fietta, Edoardo Baiesi and Seebacher, David and Ponton, Davide and Bevilacqua, A.}
}
@article {697,
	title = {Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers},
	journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
	year = {2025},
	pages = {1-9},
	keywords = {asymmetric Doherty, CMOS integrated circuits, Integrated circuit modeling, Modulation, Optimization, power amplifiers, power combining, Power generation, Resistance, RF DAC, series combining transformer (SCT), Switched-capacitor power amplifier (SCPA), Switching circuits, transformers, transistors, Very large scale integration},
	doi = {10.1109/TVLSI.2025.3583797},
	author = {Baiesi Fietta, Edoardo and Seebacher, David and Ponton, Davide and Bevilacqua, A.}
}
@article {715,
	title = {A Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication},
	journal = {IEEE Solid-State Circuits Letters},
	volume = {8},
	year = {2025},
	pages = {289-292},
	chapter = {289},
	keywords = {amplitude shift keying, CMOS technology, Delay-locked loop, Demodulation, Frequency shift keying, Full-duplex system, galvanic isolators, Gate drivers, Isolators, Modulation, Propagation delay, transceivers, transformers, Voltage control},
	doi = {10.1109/LSSC.2025.3611018},
	author = {Navarin, Lucrezia and Norling, Karl and Parenzan, Marco and Ruzzu, Stefano and Neviani, Andrea and Bevilacqua, A.}
}
@article {672,
	title = {Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters},
	journal = {IEEE Transactions on Microwave Theory and Techniques},
	volume = {72},
	year = {2024},
	pages = {2840-2851},
	keywords = {Baseband, Cartesian transmitter (TX), fully depleted silicon on insulator (FD-SOI) CMOS, Impedance, Internet of Things, Internet of Things (IoT), low-power radio frequency integrated circuit (RFIC) design, Mixers, Modulation, reactive passive mixer, Resistance, Voltage},
	doi = {10.1109/TMTT.2023.3341393},
	author = {Tomasin, Lorenzo and Vogrig, Daniele and Neviani, Andrea and Bevilacqua, A.}
}
@conference {679,
	title = {Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology},
	booktitle = {2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)},
	year = {2024},
	keywords = {CMOS technology, constant slope, controlled delay, Digital-to-time converter (DTC), Fractional-N PLL, integral non-linearity (INL), Modulation, Robustness, Semiconductor device modeling, Sensitivity, Silicon-on-insulator, Topology},
	doi = {10.1109/PRIME61930.2024.10559739},
	author = {Zugno, Nicol{\`o} and Bevilacqua, A.}
}
@conference {7527337,
	title = {A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior},
	booktitle = {2016 IEEE International Symposium on Circuits and Systems (ISCAS)},
	year = {2016},
	month = {May},
	pages = {702-705},
	keywords = {algorithm ciclicity, Algorithm design and analysis, bidirectional data-weighted averaging algorithm, CMOS digital integrated circuits, CMOS technology, Complexity theory, DAC, device mismatch, digital to analog converters, digital-analogue conversion, Hardware, hardware complexity, integrated circuit modelling, Mathematical model, Modulation, Multiplexing, sigma-delta modulation, sigma-delta modulators, size 65 nm, spurs immunity, Standards},
	doi = {10.1109/ISCAS.2016.7527337},
	author = {A. Celin and Gerosa, A.}
}
@conference {7168918,
	title = {Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs},
	booktitle = {2015 IEEE International Symposium on Circuits and Systems (ISCAS)},
	year = {2015},
	month = {May},
	pages = {1454-1457},
	keywords = {Algorithm design and analysis, analog-to-digital converter, Clocks, CMOS digital integrated circuits, CMOS integrated circuits, CMOS technologies, CMOS technology, data weighted averaging, DEM algorithms, dynamic element matching algorithms, hardware complexity, Heuristic algorithms, internal DAC, logic design, mismatch cancellation, Modulation, multibit sigma-delta ADC, multibit ΣΔ ADC, Noise, optimal DWA design, sigma-delta modulation, sigma-delta modulator, size 65 nm, Timing, ΣΔ modulator},
	issn = {0271-4302},
	doi = {10.1109/ISCAS.2015.7168918},
	author = {A. Celin and Gerosa, A.}
}
