<style face="normal" font="default" size="100%">Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters</style>

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<style face="normal" font="default" size="100%">Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters</style>

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47

<style face="normal" font="default" size="100%">A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs</style>

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<style face="normal" font="default" size="100%">A Novel Integrated Step-Up Hybrid Converter With Wide Conversion Ratio</style>

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<style face="normal" font="default" size="100%">A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications</style>

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<style face="normal" font="default" size="100%">A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior</style>

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<style face="normal" font="default" size="100%">Step-Up DC-DC converters combining basic topologies with charge pump</style>