D.  Frassetto, Cabizza, S., Agostinelli, M., Garbossa, C., Spiazzi, G., Bevilacqua, A., and Neviani, A., ?Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters?, in 2025 International Conference on IC Design and Technology (ICICDT), 2025.

L.  Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., ?A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1?s?, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

S.  Marconi, Spiazzi, G., Bevilacqua, A., and Galvano, M., ?A Novel Integrated Step-Up Hybrid Converter With Wide Conversion Ratio?, IEEE Transactions on Power Electronics, vol. 35, pp. 2764-2775, 2020.

A.  Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., ?A 130-nm CMOS Dual Input-Polarity DC?DC Converter for Low-Power Applications?, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.

A.  Celin and Gerosa, A., ?A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior?, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.

G.  Spiazzi, Marconi, S., and Bevilacqua, A., ?Step-Up DC-DC converters combining basic topologies with charge pump?, in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1-6.