@conference {729,
	title = {A 5-7 GHz BiCMOS Front-End Module for WiFi 6e with 2.2 dB NF and 16 dBm PAVG at -40 dB EVM},
	booktitle = {2025 20th European Microwave Integrated Circuits Conference (EuMIC)},
	year = {2025},
	keywords = {802.11ax, Access Point, BiCMOS, BiCMOS integrated circuits, Finite element analysis, Front-end, LNA, MCS11, Noise, Noise figure, PA, power amplifiers, receivers, SiGe, Silicon germanium, SPDT, Switch, Switching circuits, Wideband, WiFi 6e, Wireless fidelity, WLAN},
	doi = {10.23919/EuMIC65284.2025.11234373},
	author = {Pecile, Davide and Pollin, Andrea and Maistro, Daniele Dal and Gambarucci, Alberto and De Astis, Giuseppe and Bevilacqua, A.}
}
@conference {719,
	title = {Analysis of a gm-C Complex Filter for Low Power Wireless Receivers},
	booktitle = {2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME)},
	year = {2025},
	keywords = {Analytical models, BLE, CMOS technology, complex filter, Integrated circuit modeling, Linearity, Mathematical models, Noise, Power filters, receivers, Semiconductor device modeling, subthreshold, Topology, ultra-low power, Voltage, Wireless communication},
	doi = {10.1109/PRIME66228.2025.11203317},
	author = {Guglielmini, Lorenzo and Bevilacqua, A.}
}
@conference {7313827,
	title = {A 12GHz 22dB-gain-control SiGe bipolar VGA with 2{\textdegree} phase shift variation},
	booktitle = {European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st},
	year = {2015},
	month = {Sept},
	pages = {56-59},
	keywords = {bandwidth 10 GHz to 14.4 GHz, frequency 12 GHz, Gain, gain 22 dB, gain 9 dB to 13 dB, gain control, gain control SiGe bipolar VGA, Gain measurement, Ge-Si alloys, microwave phase shifters, Noise, phase shift variation, Phased arrays, power 83 mW, SiGe, SiGe bipolar technology, Silicon germanium, transistors, variable gain amplifier},
	issn = {1930-8833},
	doi = {10.1109/ESSCIRC.2015.7313827},
	author = {Padovan, F. and Tiebout, M. and Neviani, A. and Bevilacqua, A.}
}
@conference {7168918,
	title = {Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs},
	booktitle = {2015 IEEE International Symposium on Circuits and Systems (ISCAS)},
	year = {2015},
	month = {May},
	pages = {1454-1457},
	keywords = {Algorithm design and analysis, analog-to-digital converter, Clocks, CMOS digital integrated circuits, CMOS integrated circuits, CMOS technologies, CMOS technology, data weighted averaging, DEM algorithms, dynamic element matching algorithms, hardware complexity, Heuristic algorithms, internal DAC, logic design, mismatch cancellation, Modulation, multibit sigma-delta ADC, multibit ΣΔ ADC, Noise, optimal DWA design, sigma-delta modulation, sigma-delta modulator, size 65 nm, Timing, ΣΔ modulator},
	issn = {0271-4302},
	doi = {10.1109/ISCAS.2015.7168918},
	author = {A. Celin and Gerosa, A.}
}
