@article {735,
	title = {On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {73},
	year = {2026},
	month = {March},
	pages = {1777-1786},
	abstract = {Despite extensive research, the upconversion of 1/f noise into phase noise in harmonic oscillators is still an open topic of investigation. A few upconversion mechanisms are not fully understood yet. In particular, in class-B CMOS oscillators, the reason why a large tail capacitance combined with transistors entering the triode region for a portion of the oscillation cycle dramatically amplifies the 1/f noise upconversion has not been clearly pinpointed. This work introduces a simple yet powerful model to fully capture the 1/f noise upconversion mechanism. It shows that when the transistors enter the triode region, charge sharing between the tail capacitance and the tank capacitance injects a noise charge into the tank, generating phase noise perturbations quantified by the impulse sensitivity function. The analytical description results in closed-form equations that predict the $1/f^3$ phase noise sideband accurately, without relying on complex harmonic analysis or specific device nonlinearities. The excellent agreement with simulations performed both using idealized and real 55nm CMOS transistor models confirms the validity and robustness of the proposed framework, offering new insights and practical design guidelines for low phase noise CMOS oscillators.},
	keywords = {1/f noise, Capacitance, Circuits, CMOS oscillators, Equivalent circuits, Harmonic analysis, Impulse sensitivity function, Integrated circuit modeling, Perturbation methods, phase noise, Semiconductor device modeling, transistors},
	issn = {1558-0806},
	doi = {10.1109/TCSI.2025.3602924},
	author = {Bevilacqua, A. and Mazzanti, Andrea}
}
@conference {726,
	title = {Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter},
	booktitle = {2025 IEEE Nordic Circuits and Systems Conference (NorCAS)},
	year = {2025},
	keywords = {Accuracy, Analog design, Analytical models, CMOS, CMOS technology, DC-DC power converters, high-frequency operation, hybrid DC-DC converters, integrated converters, Semiconductor device modeling, Solid modeling, Switches, Switching circuits, Switching loss, switching losses, switching transients, Transient analysis},
	doi = {10.1109/NorCAS66540.2025.11231302},
	author = {Frassetto, Domenico and Cabizza, Stefano and Karim, Asif and Spiazzi, Giorgio and Bevilacqua, A. and Neviani, Andrea}
}
@conference {719,
	title = {Analysis of a gm-C Complex Filter for Low Power Wireless Receivers},
	booktitle = {2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME)},
	year = {2025},
	keywords = {Analytical models, BLE, CMOS technology, complex filter, Integrated circuit modeling, Linearity, Mathematical models, Noise, Power filters, receivers, Semiconductor device modeling, subthreshold, Topology, ultra-low power, Voltage, Wireless communication},
	doi = {10.1109/PRIME66228.2025.11203317},
	author = {Guglielmini, Lorenzo and Bevilacqua, A.}
}
@conference {703,
	title = {Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters},
	booktitle = {2025 International Conference on IC Design and Technology (ICICDT)},
	year = {2025},
	keywords = {Accuracy, Analog design, Analytical models, Buck converters, CMOS, High frequency, highfrequency operation, hybrid DC-DC converters, Hybrid power systems, Integrated circuit modeling, integrated converters, Semiconductor device modeling, Standards, Topology, Voltage},
	doi = {10.1109/ICICDT65192.2025.11078092},
	author = {Frassetto, Domenico and Cabizza, Stefano and Agostinelli, Matteo and Garbossa, Cristian and Spiazzi, Giorgio and Bevilacqua, A. and Neviani, Andrea}
}
@conference {718,
	title = {A DLL-Based FSK Demodulator for Asynchronous Communications},
	booktitle = {2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME)},
	year = {2025},
	keywords = {Asynchronous communication, asynchronous communications, Clocks, CMOS, CMOS technology, delaylocked loop, Demodulation, Frequency shift keying, frequency-shift keying (FSK), phase locked loops, Power demand, Semiconductor device modeling, Tracking loops, Wireless communication, wireline communication},
	doi = {10.1109/PRIME66228.2025.11203677},
	author = {Navarin, Lucrezia and Neviani, Andrea and Bevilacqua, A.}
}
@conference {679,
	title = {Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology},
	booktitle = {2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)},
	year = {2024},
	keywords = {CMOS technology, constant slope, controlled delay, Digital-to-time converter (DTC), Fractional-N PLL, integral non-linearity (INL), Modulation, Robustness, Semiconductor device modeling, Sensitivity, Silicon-on-insulator, Topology},
	doi = {10.1109/PRIME61930.2024.10559739},
	author = {Zugno, Nicol{\`o} and Bevilacqua, A.}
}
@conference {695,
	title = {On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers},
	booktitle = {2024 IEEE Nordic Circuits and Systems Conference (NorCAS)},
	year = {2024},
	keywords = {Analytical models, asymmetric Doherty, Circuits and systems, CMOS integrated circuits, CMOS technology, Integrated circuits, power amplifiers, power combining, Power generation, RF DAC, Semiconductor device modeling, Switched-capacitor power amplifier (SCPA), Switches, Switching circuits},
	doi = {10.1109/NorCAS64408.2024.10752466},
	author = {Fietta, Edoardo Baiesi and Seebacher, David and Ponton, Davide and Bevilacqua, A.}
}
@conference {6872748,
	title = {A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers},
	booktitle = {2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)},
	year = {2014},
	month = {June},
	pages = {1-4},
	keywords = {back-of-the-envelope equations, C-DAC, CMOS analogue integrated circuits, CMOS integrated circuits, DPA, efficiency, Equations, Integrated circuit modeling, intrinsic power, linear model, low-power CMOS technology, Mathematical model, output stage inverter, PA, power, Radio frequency, radio-frequency switched-capacitor power amplifiers, radiofrequency power amplifiers, RF-DAC, SCPA, Semiconductor device modeling, size 28 nm, SpectreRF simulations, switched capacitor networks, Switches, target output power},
	doi = {10.1109/PRIME.2014.6872748},
	author = {Passamani, A and Ponton, D. and Knoblinger, G. and Bevilacqua, A.}
}
