@conference {957696,
	title = {A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization},
	booktitle = {Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on},
	volume = {2},
	year = {2001},
	pages = {1099 -1102 vol.2},
	keywords = {0.35 micron, 0.35 mu, 300 MHz, 700 mW, analogue integrated circuits, anti-alias filter, bandwidth tunability, bit error rate, circuit bandwidth, CMOS memory circuits, CMOS technology, data rate, digital simulation, disc drives, equalisers, equalizer, fractionally spaced equalization, frequency errors, hard discs, hard disk drives, m, MATLAB, memory architecture, power consumption, pulse shaping circuits, pulse shaping precision, sampled data circuits, sampling phase, storage density, variable delay filter},
	doi = {10.1109/ICECS.2001.957696},
	author = {Gerosa, A. and Neviani, A. and Xotta, A. and Mian, G.A.}
}
