@article {665,
	title = {Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs},
	journal = {IEEE Journal of Solid-State Circuits},
	volume = {59},
	year = {2024},
	pages = {294-306},
	keywords = {CMOS, coupled phase-locked loop (CPLL), Couplings, Harmonic analysis, Mixers, phase locked loops, phase noise, quadrature voltage-controlled oscillator (QVCO), radio frequency integrated circuits (RFIC), Steady-state, voltage-controlled oscillators},
	doi = {10.1109/JSSC.2023.3280360},
	author = {Iesurum, Agata and Manente, Davide and Padovan, Fabio and Bassi, Matteo and Bevilacqua, A.}
}
@article {639,
	title = {A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {70},
	year = {2023},
	pages = {607-617},
	doi = {10.1109/TCSI.2022.3221161},
	author = {Manente, Davide and Quadrelli, Fabio and Padovan, Fabio and Bassi, Matteo and Mazzanti, Andrea and Bevilacqua, A.}
}
@conference {632,
	title = {A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS},
	booktitle = {ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)},
	year = {2022},
	doi = {10.1109/ESSCIRC55480.2022.9911510},
	author = {Iesurum, Agata and Manente, Davide and Padovan, Fabio and Bassi, Matteo and Bevilacqua, A.}
}
@article {586,
	title = {A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications},
	journal = {IEEE Journal of Solid-State Circuits},
	volume = {57},
	year = {2022},
	pages = {1968-1981},
	doi = {10.1109/JSSC.2022.3161846},
	author = {Quadrelli, Fabio and Manente, Davide and Seebacher, David and Padovan, Fabio and Bassi, Matteo and Mazzanti, Andrea and Bevilacqua, A.}
}
