<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Dartizio, Simone Mattia</style></author><author><style face="normal" font="default" size="100%">Buccoleri, Francesco</style></author><author><style face="normal" font="default" size="100%">Tesolin, Francesco</style></author><author><style face="normal" font="default" size="100%">Avallone, Luca</style></author><author><style face="normal" font="default" size="100%">Santiccioli, Alessio</style></author><author><style face="normal" font="default" size="100%">Iesurum, Agata</style></author><author><style face="normal" font="default" size="100%">Steffan, Giovanni</style></author><author><style face="normal" font="default" size="100%">Cherniak, Dmytro</style></author><author><style face="normal" font="default" size="100%">Bertulessi, Luca</style></author><author><style face="normal" font="default" size="100%">Bevilacqua, A.</style></author><author><style face="normal" font="default" size="100%">Samori, Carlo</style></author><author><style face="normal" font="default" size="100%">Lacaita, Andrea Leonardo</style></author><author><style face="normal" font="default" size="100%">Levantino, Salvatore</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching</style></title><secondary-title><style face="normal" font="default" size="100%">2022 IEEE International Solid- State Circuits Conference (ISSCC)</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2022</style></year></dates><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>