@article {6939739,
	title = {A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {62},
	number = {2},
	year = {2015},
	month = {Feb},
	pages = {413-422},
	keywords = {CMOS, Frequency conversion, frequency divider, frequency division, Harmonic analysis, harmonic rejection, phase locked loops, Radar imaging, receivers, stepped frequency continuous wave (SFCW), transmitters, UWB transmitter},
	issn = {1549-8328},
	doi = {10.1109/TCSI.2014.2362332},
	author = {Caruso, M. and Bassi, M. and Bevilacqua, A. and Neviani, A.}
}
@conference {4253094,
	title = {Quadrature VCOs Based on Coupled PLLs},
	booktitle = {IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007},
	year = {2007},
	pages = {2140 -2143},
	keywords = {0.13 micron, CMOS digital integrated circuits, coupled PLL, digital CMOS technology, dual-mode quadrature VCO, phase locked loops, quadrature signal generation, voltage-controlled oscillators},
	doi = {10.1109/ISCAS.2007.378596},
	author = {Bevilacqua, A. and Sandner, C. and Gerosa, A. and Neviani, A.}
}
