@conference {5619752,
	title = {A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request},
	booktitle = {Proceedings of the ESSCIRC 2010},
	year = {2010},
	pages = {498 -501},
	keywords = {amplitude shift keying, bit rate 5 Mbit/s, CMOS analogue integrated circuits, frequency 5.4 GHz, frequency 7.25 GHz to 8.5 GHz, LNA, low noise amplifiers, OOK modulation, PPM modulation, pulse polarity scrambling, pulsed transmitter, size 130 nm, squarer, transceivers, UWB-IR CMOS transceiver, VGA, windowed integrator},
	issn = {1930-8833},
	doi = {10.1109/ESSCIRC.2010.5619752},
	author = {Sold{\`a}, S. and Caruso, M. and Bevilacqua, A. and Gerosa, A. and Vogrig, D. and Neviani, A.}
}
@conference {4242444,
	title = {A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers},
	booktitle = {Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference},
	year = {2007},
	pages = {420 -612},
	keywords = {0.13 micron, 19.4 dB, 24 mW, 3 to 5 GHz, 7.5 mW, baluns, CMOS analogue integrated circuits, CMOS LNA, integrated balun, integrated notch filter, ISM band, low noise amplifiers, microwave integrated circuits, microwave receivers, notch filters, radio receivers, ultra wideband technology, UNII band, UWB receivers, WLAN blockers},
	issn = {0193-6530},
	doi = {10.1109/ISSCC.2007.373473},
	author = {Bevilacqua, A. and Vallese, A. and Sandner, C. and Tiebout, M. and Gerosa, A. and Neviani, A.}
}
@conference {4430265,
	title = {An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS},
	booktitle = {Proc. of IEEE 2007 European Solid State Circuits Conference},
	year = {2007},
	pages = {139 -142},
	keywords = {analog front-end, automatic tuning, CMOS, CMOS analogue integrated circuits, current 20 mA, frequency 3 GHz to 5 GHz, integrated notch filter, microwave filters, MMIC, notch filters, out-of-band blockers, power consumption penalty, radio receivers, size 0.13 mum, ultra wideband communication, UWB receivers, voltage 1.5 V},
	issn = {1930-8833},
	doi = {10.1109/ESSCIRC.2007.4430265},
	author = {Vallese, A. and Bevilacqua, A. and Sandner, C. and Tiebout, M. and Gerosa, A. and Neviani, A.}
}
@article {4012490,
	title = {Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code},
	journal = {Communications, IEEE Transactions on},
	volume = {54},
	number = {11},
	year = {2006},
	pages = {1973 -1982},
	keywords = {0.35 micron, 3.3 V, 3G mobile communication, bit-error rate, block length-40 UMTS turbo code, circuit transient behavior, CMOS analog decoder, CMOS analogue integrated circuits, component mismatch, decoding, discrete time systems, discrete-time first-order model, error statistics, fast BER simulation, integrated circuit design, integrated circuit testing, Third Generation Partnership Project standard, transistor-level simulation, turbo codes, universal mobile telecommunications system},
	issn = {0090-6778},
	doi = {10.1109/TCOMM.2006.884836},
	author = {Graell i Amat, A. and Benedetto, S. and Montorsi, G. and Vogrig, D. and Neviani, A. and Gerosa, A.}
}
@conference {4263311,
	title = {A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency},
	booktitle = {13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS {\textquoteright}06. },
	year = {2006},
	pages = {90 -93},
	keywords = {bandwidth 14 kHz to 150 kHz, circuit tuning, class AB operation filter, CMOS analogue integrated circuits, CMOS process, CMOS technology, low-pass filter, low-pass filters, low-power electronics, low-voltage filter, parasitic capacitances effect, size 0.8 mum, third-order log-domain filter, tunable frequency, voltage 1.2 V},
	doi = {10.1109/ICECS.2006.379708},
	author = {Maniero, A. and Bevilacqua, A. and Gerosa, A. and Neviani, A.}
}
@article {1408096,
	title = {A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code},
	journal = {Solid-State Circuits, IEEE Journal of},
	volume = {40},
	number = {3},
	year = {2005},
	pages = {753 - 762},
	keywords = {0.35 micron, 10.3 mW, 2 Mbit/s, 2 V, 3.3 V, 3G mobile communication, 40 bit, 7.6 mW, analog decoder, analog iterative decoders, channel coding, CMOS analog turbo decoder, CMOS analogue integrated circuits, decoder throughput, error correction codes, error-correcting code, I/O interface, iterative decoding, neuromorphic circuits, translinear circuits, turbo code, turbo codes, UMTS channel code, weak inversion},
	issn = {0018-9200},
	doi = {10.1109/JSSC.2005.843628},
	author = {Vogrig, D. and Gerosa, A. and Neviani, A. and Amat, A.Gi. and Montorsi, G. and Benedetto, S.}
}
@conference {1542996,
	title = {A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code},
	booktitle = {Research in Microelectronics and Electronics, 2005 PhD},
	volume = {1},
	year = {2005},
	pages = {31 - 34 vol.1},
	keywords = {0.35 micron, 1.36 nJ, 132 bit, 2 Mbit/s, 3G mobile communication, 3GPP standard, 40 bit, 6.6 mW, channel coding, CMOS analog turbo decoder, CMOS analogue integrated circuits, concatenated codes, parallel concatenated code, turbo codes, UMTS channel code, wireless data transmission systems},
	doi = {10.1109/RME.2005.1542996},
	author = {Vogrig, D. and Gerosa, A. and Neviani, A. and Graell i Amat, A. and Montorsi, G. and Benedetto, S.}
}
@conference {1494434,
	title = {An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code},
	booktitle = {Communications, 2005. ICC 2005. 2005 IEEE International Conference on},
	volume = {1},
	year = {2005},
	pages = {663 - 667 Vol. 1},
	keywords = {0.35 micron, 10.3 mW, 2 Mbit/s, 3.3 V, 3G mobile communication, 40 bit, analog turbo decoder, BER curve, circuit simulation, circuit transient behavior, circuit-level simulations, CMOS analogue integrated circuits, CMOS turbo decoder, device mismatch, discrete-time model, error statistics, iterative decoding, rate-1/3 turbo code, turbo codes, UMTS turbo code},
	doi = {10.1109/ICC.2005.1494434},
	author = {Amatt, A.G.I. and Benedetto, S. and Montorsi, G. and Vogrig, D. and Neviani, A. and Gerosa, A.}
}
@conference {1365329,
	title = {An analog turbo decoder for the UMTS standard},
	booktitle = {Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on},
	year = {2004},
	pages = {296},
	keywords = {0.35 micron, 3G mobile communication, CMOS analog turbo decoder, CMOS analogue integrated circuits, discrete time systems, discrete-time model, telecommunication standards, turbo codes, UMTS standard, universal mobile telecommunication system},
	doi = {10.1109/ISIT.2004.1365329},
	author = {Graell i Amat, A. and Montorsi, G. and Benedetto, S. and Vogrig, D. and Neviani, A. and Gerosa, A.}
}
@conference {1010642,
	title = {An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels},
	booktitle = {Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on},
	volume = {5},
	year = {2002},
	pages = {V-69 - V-72 vol.5},
	keywords = {0.18 micron, 1.8 V, 400 Mbit/s, 650 mW, all-analog CMOS implementation, analogue processing circuits, CMOS analogue integrated circuits, coding gain, current-mode approach, current-mode circuits, decoding, disc drives, EPR-IV read channels, hard discs, hard-disk drive read channels, power efficiency, sum-product algorithms, total simulated power consumption, turbo codes, turbo decoder},
	doi = {10.1109/ISCAS.2002.1010642},
	author = {Xotta, A. and Vogrig, D. and Gerosa, A. and Neviani, A. and Graell i Amat, A. and Montorsi, G. and Bruccoleri, M. and Betti, G.}
}
@conference {914956,
	title = {An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process},
	booktitle = {Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on},
	year = {2001},
	pages = {152 -157},
	keywords = {0.8 micron, analog front-end, analogue processing circuits, band-pass filtering, biomedical signal, biquadratic filters, cardiac pacemaker, CMOS analogue integrated circuits, CMOS process, log-domain filter, low-noise pre-amplifier, low-power design, low-power electronics, pacemakers, peak detection, preamplifiers, SC biquadratic cell, sensing chain, sigma-delta converter, sigma-delta modulation, switched capacitor filters},
	doi = {10.1109/SSMSD.2001.914956},
	author = {Gerosa, A. and Novo, A. and Neviani, A.}
}
@article {972176,
	title = {CMOS implementation of all-analogue APP decoders: analysis of performances and limitations},
	journal = {Electronics Letters},
	volume = {37},
	number = {25},
	year = {2001},
	pages = {1501 -1503},
	keywords = {a posteriori-probability decoding algorithm, analogue processing circuits, CMOS all-analogue APP decoder, CMOS analogue integrated circuits, decoding, MOS transistor, tail-biting decoder, weak inversion region},
	issn = {0013-5194},
	doi = {10.1049/el:20011025},
	author = {Xotta, A. and Gerosa, A. and Neviani, A.}
}
@conference {921851,
	title = {A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker},
	booktitle = {Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on},
	volume = {1},
	year = {2001},
	pages = {296 -299 vol. 1},
	keywords = {0.8 micron, 2.8 muW, 50 to 70 dB, active filters, cardiac pacemaker, cardiac signal, class AB log-domain 2nd order band-pass filter, CMOS, CMOS analogue integrated circuits, feedback amplifiers, input-referred noise, integrated circuit noise, low-power electronics, micro-power low noise log-domain amplifier, pacemakers, programmable gain, sensing chain, weak inversion},
	doi = {10.1109/ISCAS.2001.921851},
	author = {Gerosa, A. and Novo, A. and Mengalli, A. and Neviani, A.}
}
@conference {768617,
	title = {A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters},
	booktitle = {Mixed-Signal Design, 1999. SSMSD {\textquoteright}99. 1999 Southwest Symposium on},
	year = {1999},
	pages = {195 -198},
	keywords = {0.8 micron, 2D SC FIR filters, analogue storage, CMOS analogue integrated circuits, CMOS technology, convolution, delay efficient realization, delays, filter impulse response symmetry, filter phase linearity, FIR filters, inner filter delays, partial accumulation analog-RAM-based architecture, partial convolution products, picture-in-picture applications, random-access storage, switched capacitor filters, transient response, video applications, video signal processing},
	doi = {10.1109/SSMSD.1999.768617},
	author = {Gerosa, A. and Neviani, A. and Cortelazzo, G.M.}
}
@article {769482,
	title = {Programmable voltage multiplier for pacemaker output pulse generation},
	journal = {Electronics Letters},
	volume = {35},
	number = {7},
	year = {1999},
	pages = {560 -561},
	keywords = {circuit topology, CMOS analogue integrated circuits, CMOS IC, heart stimulation, pacemaker battery operation, pacemaker output pulse generation, pacemakers, programmable voltage multiplier, pulse generators, voltage multipliers},
	issn = {0013-5194},
	doi = {10.1049/el:19990369},
	author = {Novo, A. and Gerosa, A. and Neviani, A. and Mozzi, A. and Zanoni, E.}
}
