@article {4012490,
	title = {Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code},
	journal = {Communications, IEEE Transactions on},
	volume = {54},
	number = {11},
	year = {2006},
	pages = {1973 -1982},
	keywords = {0.35 micron, 3.3 V, 3G mobile communication, bit-error rate, block length-40 UMTS turbo code, circuit transient behavior, CMOS analog decoder, CMOS analogue integrated circuits, component mismatch, decoding, discrete time systems, discrete-time first-order model, error statistics, fast BER simulation, integrated circuit design, integrated circuit testing, Third Generation Partnership Project standard, transistor-level simulation, turbo codes, universal mobile telecommunications system},
	issn = {0090-6778},
	doi = {10.1109/TCOMM.2006.884836},
	author = {Graell i Amat, A. and Benedetto, S. and Montorsi, G. and Vogrig, D. and Neviani, A. and Gerosa, A.}
}
