<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Grimaldi, Luigi</style></author><author><style face="normal" font="default" size="100%">Iesurum, Agata</style></author><author><style face="normal" font="default" size="100%">Boi, Giovanni</style></author><author><style face="normal" font="default" size="100%">Versolatto, Fabio</style></author><author><style face="normal" font="default" size="100%">Steffan, Giovanni</style></author><author><style face="normal" font="default" size="100%">Padovan, Fabio</style></author><author><style face="normal" font="default" size="100%">Koltsov, Heorhii</style></author><author><style face="normal" font="default" size="100%">Bevilacqua, A.</style></author><author><style face="normal" font="default" size="100%">Cherniak, Dmytro</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs</style></title><secondary-title><style face="normal" font="default" size="100%">2024 IEEE European Solid-State Electronics Research Conference (ESSERC)</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">CMOS</style></keyword><keyword><style  face="normal" font="default" size="100%">Digital Phase-locked loops (DPLLs)</style></keyword><keyword><style  face="normal" font="default" size="100%">digital pre-distortion</style></keyword><keyword><style  face="normal" font="default" size="100%">digitally-controlled oscillator (DCO)</style></keyword><keyword><style  face="normal" font="default" size="100%">fast locking</style></keyword><keyword><style  face="normal" font="default" size="100%">Frequency modulation</style></keyword><keyword><style  face="normal" font="default" size="100%">frequency synthesizers</style></keyword><keyword><style  face="normal" font="default" size="100%">Jitter</style></keyword><keyword><style  face="normal" font="default" size="100%">mm-Wave</style></keyword><keyword><style  face="normal" font="default" size="100%">Phase modulation</style></keyword><keyword><style  face="normal" font="default" size="100%">Power demand</style></keyword><keyword><style  face="normal" font="default" size="100%">Prototypes</style></keyword><keyword><style  face="normal" font="default" size="100%">Spread spectrum communication</style></keyword><keyword><style  face="normal" font="default" size="100%">Standards</style></keyword><keyword><style  face="normal" font="default" size="100%">Time-frequency analysis</style></keyword><keyword><style  face="normal" font="default" size="100%">Transient analysis</style></keyword><keyword><style  face="normal" font="default" size="100%">Wireless communication</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2024</style></year></dates><language><style face="normal" font="default" size="100%">eng</style></language></record><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Buccoleri, Francesco</style></author><author><style face="normal" font="default" size="100%">Dartizio, Simone M.</style></author><author><style face="normal" font="default" size="100%">Tesolin, Francesco</style></author><author><style face="normal" font="default" size="100%">Avallone, Luca</style></author><author><style face="normal" font="default" size="100%">Santiccioli, Alessio</style></author><author><style face="normal" font="default" size="100%">Iesurum, Agata</style></author><author><style face="normal" font="default" size="100%">Steffan, Giovanni</style></author><author><style face="normal" font="default" size="100%">Cherniak, Dmytro</style></author><author><style face="normal" font="default" size="100%">Bertulessi, Luca</style></author><author><style face="normal" font="default" size="100%">Bevilacqua, A.</style></author><author><style face="normal" font="default" size="100%">Samori, Carlo</style></author><author><style face="normal" font="default" size="100%">Lacaita, Andrea L.</style></author><author><style face="normal" font="default" size="100%">Levantino, Salvatore</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Journal of Solid-State Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2023</style></year></dates><volume><style face="normal" font="default" size="100%">58</style></volume><pages><style face="normal" font="default" size="100%">634-646</style></pages><language><style face="normal" font="default" size="100%">eng</style></language></record><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Dartizio, Simone Mattia</style></author><author><style face="normal" font="default" size="100%">Buccoleri, Francesco</style></author><author><style face="normal" font="default" size="100%">Tesolin, Francesco</style></author><author><style face="normal" font="default" size="100%">Avallone, Luca</style></author><author><style face="normal" font="default" size="100%">Santiccioli, Alessio</style></author><author><style face="normal" font="default" size="100%">Iesurum, Agata</style></author><author><style face="normal" font="default" size="100%">Steffan, Giovanni</style></author><author><style face="normal" font="default" size="100%">Cherniak, Dmytro</style></author><author><style face="normal" font="default" size="100%">Bertulessi, Luca</style></author><author><style face="normal" font="default" size="100%">Bevilacqua, A.</style></author><author><style face="normal" font="default" size="100%">Samori, Carlo</style></author><author><style face="normal" font="default" size="100%">Lacaita, Andrea Leonardo</style></author><author><style face="normal" font="default" size="100%">Levantino, Salvatore</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching</style></title><secondary-title><style face="normal" font="default" size="100%">2022 IEEE International Solid- State Circuits Conference (ISSCC)</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2022</style></year></dates><language><style face="normal" font="default" size="100%">eng</style></language></record><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Buccoleri, Francesco</style></author><author><style face="normal" font="default" size="100%">Dartizio, Simone M.</style></author><author><style face="normal" font="default" size="100%">Tesolin, Francesco</style></author><author><style face="normal" font="default" size="100%">Avallone, Luca</style></author><author><style face="normal" font="default" size="100%">Santiccioli, Alessio</style></author><author><style face="normal" font="default" size="100%">Lesurum, Agata</style></author><author><style face="normal" font="default" size="100%">Steffan, Giovanni</style></author><author><style face="normal" font="default" size="100%">Bevilacqua, A.</style></author><author><style face="normal" font="default" size="100%">Bertulessi, Luca</style></author><author><style face="normal" font="default" size="100%">Cherniak, Dmytro</style></author><author><style face="normal" font="default" size="100%">Samori, Carlo</style></author><author><style face="normal" font="default" size="100%">Lacaita, Andrea L.</style></author><author><style face="normal" font="default" size="100%">Levantino, Salvatore</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler</style></title><secondary-title><style face="normal" font="default" size="100%">2022 IEEE Custom Integrated Circuits Conference (CICC)</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2022</style></year></dates><language><style face="normal" font="default" size="100%">eng</style></language></record><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Dartizio, Simone M.</style></author><author><style face="normal" font="default" size="100%">Buccoleri, Francesco</style></author><author><style face="normal" font="default" size="100%">Tesolin, Francesco</style></author><author><style face="normal" font="default" size="100%">Avallone, Luca</style></author><author><style face="normal" font="default" size="100%">Santiccioli, Alessio</style></author><author><style face="normal" font="default" size="100%">Iesurum, Agata</style></author><author><style face="normal" font="default" size="100%">Steffan, Giovanni</style></author><author><style face="normal" font="default" size="100%">Cherniak, Dmytro</style></author><author><style face="normal" font="default" size="100%">Bertulessi, Luca</style></author><author><style face="normal" font="default" size="100%">Bevilacqua, A.</style></author><author><style face="normal" font="default" size="100%">Samori, Carlo</style></author><author><style face="normal" font="default" size="100%">Lacaita, Andrea L.</style></author><author><style face="normal" font="default" size="100%">Levantino, Salvatore</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Journal of Solid-State Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2022</style></year></dates><pages><style face="normal" font="default" size="100%">1-14</style></pages><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>