@conference {688,
	title = {A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs},
	booktitle = {2024 IEEE European Solid-State Electronics Research Conference (ESSERC)},
	year = {2024},
	keywords = {CMOS, Digital Phase-locked loops (DPLLs), digital pre-distortion, digitally-controlled oscillator (DCO), fast locking, Frequency modulation, frequency synthesizers, Jitter, mm-Wave, Phase modulation, Power demand, Prototypes, Spread spectrum communication, Standards, Time-frequency analysis, Transient analysis, Wireless communication},
	doi = {10.1109/ESSERC62670.2024.10719534},
	author = {Grimaldi, Luigi and Iesurum, Agata and Boi, Giovanni and Versolatto, Fabio and Steffan, Giovanni and Padovan, Fabio and Koltsov, Heorhii and Bevilacqua, A. and Cherniak, Dmytro}
}
@article {665,
	title = {Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs},
	journal = {IEEE Journal of Solid-State Circuits},
	volume = {59},
	year = {2024},
	pages = {294-306},
	keywords = {CMOS, coupled phase-locked loop (CPLL), Couplings, Harmonic analysis, Mixers, phase locked loops, phase noise, quadrature voltage-controlled oscillator (QVCO), radio frequency integrated circuits (RFIC), Steady-state, voltage-controlled oscillators},
	doi = {10.1109/JSSC.2023.3280360},
	author = {Iesurum, Agata and Manente, Davide and Padovan, Fabio and Bassi, Matteo and Bevilacqua, A.}
}
