@conference {4150707,
	title = {CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code},
	booktitle = {Global Telecommunications Conference, 2006. GLOBECOM {\textquoteright}06. IEEE},
	year = {2006},
	pages = {1 -6},
	keywords = {analog iterative decoder, analog memory, block length, code rate, concatenated codes, convolutional codes, interleaved codes, iterative decoding, performance mismatch impact, reconfigurable analog decoder, reconfigurable interleaver, serially concatenated convolutional code, single-input single-output, SISO decoder, trellis code, trellis codes},
	issn = {1930-529X},
	doi = {10.1109/GLOCOM.2006.77},
	author = {Graell i Amat, A. and Vogrig, D. and Benedetto, S. and Montorsi, G. and Neviani, A. and Gerosa, A.}
}
