F.  Chiocchetta, De Santi, C., Rampazzo, F., Mukherjee, K., Grünenpütt, J., Sommer, D., Blanck, H., Lambert, B., Gerosa, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., ?GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse?, in 2022 IEEE International Reliability Physics Symposium (IRPS), 2022.

D.  Vogrig, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A Symbol-Duty-Cycled 440-pJ/b Impulse Radio Receiver With 0.57-aJ Sensitivity in 130-nm CMOS?, IEEE Transactions on Microwave Theory and Techniques, vol. 65, pp. 565-573, 2017.

A.  Celin and Gerosa, A., ?A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior?, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.

A.  Celin and Gerosa, A., ?Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ?? ADCs?, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1454-1457.

D.  Vogrig, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A symbol-duty-cycled 440 pJ/b impulse radio receiver with 0.57 aJ sensitivity in 130 nm CMOS?, in Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE, 2015, pp. 243-246.

M.  Bassi, Bevilacqua, A., Gerosa, A., and Neviani, A., ?Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints?, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, pp. 1228 -1241, 2012.

A.  Gerosa, Bevilacqua, A., and Neviani, A., ?A local oscillator for WCDMA band VII based on frequency multiplication?, Analog Integrated Circuits and Signal Processing, vol. 72, no. 1, 2012.

S.  Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., ?A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13um CMOS?, IEEE Journal of Solid-State Circuits, vol. 46, pp. 1636 -1647, 2011.

M.  Bassi, Bevilacqua, A., Gerosa, A., and Neviani, A., ?Integrated Transceivers for UWB Breast Cancer Imaging: Architecture and Circuit Constraints?, in 2011 IEEE International Symposium on Circuits and Systems, 2011, pp. 2087-2090.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS?, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.

A.  Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., ?A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS?, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.

S.  Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., ?A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request?, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.

A.  Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., ?A digitally programmable ring oscillator in the UWB range?, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),, 2010, pp. 1101 -1104.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands S Through Ku?, IEEE Transactions on Microwave Theory and Techniques, vol. 58, pp. 1686 -1695, 2010.

S.  Soldà, Caruso, M., Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., ?Low-power UWB transmitter using a combined mixer and power amplifier?, in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 333 -336.

S.  Dal Toso, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks?, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 1903 -1906.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS?, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.

A.  Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems?, IEEE Journal of Solid-State Circuits, vol. 44, pp. 331 -343, 2009.

A.  Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., ?An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 1030 -1040, 2009.

A.  Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS?, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.

S.  Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., ?Analog decoding of trellis coded modulation for multi-level flash memories?, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.

A.  Bevilacqua, Camponeschi, M., Tiebout, M., Gerosa, A., and Neviani, A., ?Design of broadband inductorless LNAs in ultra-scaled CMOS technologies?, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008. , 2008, pp. 1300 -1303.

A.  Gerosa, Costa, M. D., Bevilacqua, A., Vogrig, D., and Neviani, A., ?An energy-detector for non-coherent impulse-radio UWB receivers?, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008, 2008, pp. 2705 -2708.

S. D.  Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, in Digest of Technical Papers of 2008 IEEE International Solid-State Circuits Conference, 2008, pp. 124 -601.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2844 -2852, 2008.

A.  Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers?, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.

A.  Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., ?A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver?, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.

A.  Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS?, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.

A.  Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., ?An Integrated Solution for Suppressing WLAN Signals in UWB Receivers?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, pp. 1617 -1625, 2007.

A.  Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., ?Quadrature VCOs Based on Coupled PLLs?, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 2140 -2143.

A.  Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., ?Transformer-Based Dual-Mode Voltage-Controlled Oscillators?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, pp. 293 -297, 2007.

A.  Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., ?A 0.35 um SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection?, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 1015 -1018.

A.  Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., ?A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO?, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

A.  Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., ?An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling ? ? Modulator and a Flash Converter?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.

A.  Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., Neviani, A., and Gerosa, A., ?CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code?, in Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE, 2006, pp. 1 -6.

A.  Graell i Amat, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., ?Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code?, Communications, IEEE Transactions on, vol. 54, pp. 1973 -1982, 2006.

A.  Gerosa, Elettronica Digitale, Esercizi risolti. PADOVA: Edizioni Libreria Progetto, 2006, pp. 1?216.

A.  Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., ?A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers?, IEEE Microwave and Wireless Components Letters, vol. 16, pp. 134 -136, 2006.

A.  Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., SOLDA, S., Neviani, A., and Gerosa, A., ?Iterative Analog Decoder for a SCCC?, in Analog Decoding Workshop, 2006.

A.  Maniero, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency?, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 90 -93.

A.  Gerosa, Bevilacqua, A., Neviani, A., and Xotta, A., ?An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter?, in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, 2006, p. 4 pp.

D.  Vogrig, Gerosa, A., Neviani, A., Amat, A. G., Montorsi, G., and Benedetto, S., ?A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code?, Solid-State Circuits, IEEE Journal of, vol. 40, pp. 753 - 762, 2005.

D.  Vogrig, Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., and Benedetto, S., ?A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code?, in Research in Microelectronics and Electronics, 2005 PhD, 2005, vol. 1, pp. 31 - 34 vol.1.

A.  Gerosa and Neviani, A., ?A 1.8uW Sigma-Delta Modulator for 8-bit Digitization of Cardiac Signals in Implantable Pacemakers Operating Down to 1.8V?, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, vol. 52, pp. 71?76, 2005.

A. G. I.  Amatt, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., ?An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code?, in Communications, 2005. ICC 2005. 2005 IEEE International Conference on, 2005, vol. 1, pp. 663 - 667 Vol. 1.

A.  Xotta, Gerosa, A., and Neviani, A., ?A Multi-Mode Sigma-Delta Analog-to-Digital Converter for GSM, UMTS and WLAN?, in ISCAS, 2005.

A.  Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., ?An analog turbo decoder for the UMTS standard?, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.

A.  Gerosa, Elettronica Digitale, Esercizi Risolti. PADOVA ? ITA: Libreria Progetto, 2004, pp. 1?161.

A.  Gerosa, Maniero, A., and Neviani, A., ?A Fully-Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemakers?, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 51, pp. 1916?1925, 2004.

A.  Gerosa, Neviani, A., and Maniero, A., ?A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers?, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, pp. 1083?1093, 2004.

A.  Gerosa and Neviani, A., ?A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER?, in ISCAS, 2004, vol. 2, pp. 245?248.

A.  Xotta, Gerosa, A., and Neviani, A., ?A Programmable-Order Sigma-Delta Converter for a Multi-Standard Wireless Receiver?, in WowCas, Vancouver B.C., Canada, 2004, vol. 1, pp. 33?34.

M.  PERENZONI, Gerosa, A., and Neviani, A., ?Analog CMOS Implementation of Gallager?s Interative Decoding algorithm applied to a Block Turbo Code?, in ISCAS, 2003, vol. 5, pp. 813?816.

A.  Gerosa and Neviani, A., ?Enhancing Output Voltage Swing in Low-Voltage Micro-Power OTA Using Self-Cascode?, ELECTRONICS LETTERS, vol. 39, pp. 638?639, 2003.

A.  Gerosa, Xotta, A., Neviani, A., and Mian, G. A., ?Frequency Offset Compensation in Fractionally Spaced Equalization?, IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS, vol. 150, pp. 134?140, 2003.

A.  Gerosa, Maniero, A., and Neviani, A., ?A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers?, in ESSCIRC, 2003, vol. 1, pp. 157?160.

A.  Maniero, Gerosa, A., and Neviani, A., ?Performance Optimization in Micro-Power, Low-Voltage, Log-Domain Filters in Pure CMOS Technology?, in ISCAS, 2003, vol. 1, pp. 565?568.

A.  Gerosa and Neviani, A., ?A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V?, in ISCAS, 2003, vol. 5, pp. 49?52.

A.  Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., ?An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels?, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.

A.  Gerosa, Bernardini, R., and Pietri, S., ?A Fully Integrated Chaotic System for the Generation of Truly Random Numbers?, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, vol. 49, pp. 993?1000, 2002.

A.  Gerosa, Novo, A., and Neviani, A., ?An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process?, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.

A.  Xotta, Gerosa, A., and Neviani, A., ?CMOS implementation of all-analogue APP decoders: analysis of performances and limitations?, Electronics Letters, vol. 37, pp. 1501 -1503, 2001.

A.  Gerosa, ?Design of Power-Optimized OTAs for SC Applications?. 2001.

A.  Gerosa, Bernardini, R., and Pietri, S., ?A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system?, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 87 -92.

A.  Gerosa, Novo, A., Mengalli, A., and Neviani, A., ?A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker?, in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001, vol. 1, pp. 296 -299 vol. 1.

A.  Gerosa, Neviani, A., Xotta, A., and Mian, G. A., ?A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization?, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 1099 -1102 vol.2.

A.  Gerosa, ?A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption?, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 949 -952 vol.2.

A.  Gerosa, RUBIN, R., and Neviani, A., ?A Simplified Analysis of Noise in Switched Capacitor Networks from a Circuit Design Perspective?, in ECCTD, 2001, vol. 1, pp. 261?264.

A.  Novo, Gerosa, A., and Neviani, A., ?A Sub-Micron CMOS Programmable Charge Pump for Implantable Pacemaker?, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol. 27, pp. 211?217, 2001.

A.  Novo, Gerosa, A., Neviani, A., Mozzi, A., and Zanoni, E., ?A CMOS 0.8 um programmable charge pump for the output stage of an implantable pacemaker?, in Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on, 2000, pp. 34/1 -34/5.

A.  Gerosa, Novo, A., and Neviani, A., ?Low-power sensing and digitization of cardiac signals based on sigma-delta conversion?, in Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on, 2000, pp. 216 - 218.

A.  Gerosa, Cortelazzo, G. M., Baschirotto, A., and Malavasi, E., ?2D video rate SC FIR filters based on analog RAMs?, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 46, pp. 1348 -1360, 1999.

A.  Gerosa and Mian, G. A., ?A low complexity EPR-IV equalizer for hard disk read channels?, in Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on, 1999, vol. 2, pp. 1069 -1072 vol.2.

A.  Gerosa, Neviani, A., and Cortelazzo, G. M., ?A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters?, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.

A.  Novo, Gerosa, A., Neviani, A., Mozzi, A., and Zanoni, E., ?Programmable voltage multiplier for pacemaker output pulse generation?, Electronics Letters, vol. 35, pp. 560 -561, 1999.

A.  Novo, Gerosa, A., Neviani, A., Zanoni, E., and Mozzi, A., ?Programmable voltage multipliers for pacemaker output pulse generation in CMOS 0.8 um technology?, in Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European, 1999, pp. 386 - 389.

A.  Gerosa, Neviani, A., and Zanoni, E., ?A SC Video Filter with Analog-RAM-based Delay Efficient Realization?, in ECCTD, 1999, vol. 2, pp. 1247?1250.

G.  MENEGHESSO, Zanoni, E., Gerosa, A., PAVAN, P., STADLER, W., ESMARK, K., and GUGGENMOS, G., ?Test structures and testing methods for electrostatic discharge: results of PROPHECY project?, MICROELECTRONICS RELIABILITY, vol. 39, pp. 635?646, 1999.

A.  Gerosa and Mian, G. A., ?An Equalizer for Hard Disk Drive Channels, with Low Sensitivity to Sampling Phase Variation?, in EUSIPCO-98, 1998, vol. 1, pp. 483?486.

G. M.  Cortelazzo, Malavasi, E., Gerosa, A., and Neviani, A., ?A New Structure for Video-Rate 2D SC FIR Filters?, in EUSIPCO-96, 1996, vol. 2, pp. 1307?1310.