@article {1710191,
	title = {An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {53},
	number = {10},
	year = {2006},
	pages = {2109 -2124},
	keywords = {18.9 mW, 3G mobile communication, 4 bit, 4.6 mW, 5.5 mW, 7.4 mW, analog-to-digital converter, analogue-digital conversion, behavioral simulations, Bluetooth, cellular radio, double-sampling SigmaDelta modulator, flash converter, global system for mobile communications, internal quantizer, multimode wireless receivers, radio receivers, transistor-level simulations, universal mobile telecommunications system, wireless LAN, wireless local area network},
	issn = {1549-8328},
	doi = {10.1109/TCSI.2006.883840},
	author = {Gerosa, A. and Xotta, A. and Bevilacqua, A. and Neviani, A.}
}
@conference {914944,
	title = {A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system},
	booktitle = {Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on},
	year = {2001},
	pages = {87 -92},
	keywords = {0.8 micron, 20 MHz, 50 mW, 8 bit, analogue-digital conversion, ASIC, chaos generators, chaotic system, circuit nonidealities, CMOS integrated circuits, CMOS process, compact architecture, fully integrated implementation, mixed analogue-digital integrated circuits, pipeline ADC, pipeline processing, post-layout simulations, random number generation, random numbers generator, statistical independence, uniform distribution},
	doi = {10.1109/SSMSD.2001.914944},
	author = {Gerosa, A. and Bernardini, R. and Pietri, S.}
}
@conference {813418,
	title = {A low complexity EPR-IV equalizer for hard disk read channels},
	booktitle = {Electronics, Circuits and Systems, 1999. Proceedings of ICECS {\textquoteright}99. The 6th IEEE International Conference on},
	volume = {2},
	year = {1999},
	pages = {1069 -1072 vol.2},
	keywords = {0.35 mum, ADC accuracy, analogue-digital conversion, area consumption, BRE, circuit design, circuit simulation, CMOS integrated circuits, complexity, digital post-processing, equalisers, equalization performance, FIR filters, fractionally spaced equalization, hard discs, hard disk read channels, low complexity EPR-IV equalizer, memory architecture, network synthesis, power consumption, sampled data, sampled data circuits, standard CMOS, transistor level simulation},
	doi = {10.1109/ICECS.1999.813418},
	author = {Gerosa, A. and Mian, G.A.}
}
