@conference {7527337,
	title = {A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior},
	booktitle = {2016 IEEE International Symposium on Circuits and Systems (ISCAS)},
	year = {2016},
	month = {May},
	pages = {702-705},
	keywords = {algorithm ciclicity, Algorithm design and analysis, bidirectional data-weighted averaging algorithm, CMOS digital integrated circuits, CMOS technology, Complexity theory, DAC, device mismatch, digital to analog converters, digital-analogue conversion, Hardware, hardware complexity, integrated circuit modelling, Mathematical model, Modulation, Multiplexing, sigma-delta modulation, sigma-delta modulators, size 65 nm, spurs immunity, Standards},
	doi = {10.1109/ISCAS.2016.7527337},
	author = {A. Celin and Gerosa, A.}
}
@conference {7168918,
	title = {Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs},
	booktitle = {2015 IEEE International Symposium on Circuits and Systems (ISCAS)},
	year = {2015},
	month = {May},
	pages = {1454-1457},
	keywords = {Algorithm design and analysis, analog-to-digital converter, Clocks, CMOS digital integrated circuits, CMOS integrated circuits, CMOS technologies, CMOS technology, data weighted averaging, DEM algorithms, dynamic element matching algorithms, hardware complexity, Heuristic algorithms, internal DAC, logic design, mismatch cancellation, Modulation, multibit sigma-delta ADC, multibit ΣΔ ADC, Noise, optimal DWA design, sigma-delta modulation, sigma-delta modulator, size 65 nm, Timing, ΣΔ modulator},
	issn = {0271-4302},
	doi = {10.1109/ISCAS.2015.7168918},
	author = {A. Celin and Gerosa, A.}
}
@conference {1692653,
	title = {An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter},
	booktitle = {Proceedings of 2006 IEEE International Symposium on Circuits and Systems},
	year = {2006},
	pages = {4 pp.},
	keywords = {18.9 mW, 3G mobile communication, 4 bit, 4.6 mW, 5.5 mW, 7.4 mW, Bluetooth, cellular radio, flash converter, GSM, internal quantizer, multimode ADC, optimal architecture, power consumption, sigma-delta modulation, sigma-delta modulator, UMTS, wireless LAN, WLANa},
	doi = {10.1109/ISCAS.2006.1692653},
	author = {Gerosa, A. and Bevilacqua, A. and Neviani, A. and Xotta, A.}
}
@conference {914956,
	title = {An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process},
	booktitle = {Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on},
	year = {2001},
	pages = {152 -157},
	keywords = {0.8 micron, analog front-end, analogue processing circuits, band-pass filtering, biomedical signal, biquadratic filters, cardiac pacemaker, CMOS analogue integrated circuits, CMOS process, log-domain filter, low-noise pre-amplifier, low-power design, low-power electronics, pacemakers, peak detection, preamplifiers, SC biquadratic cell, sensing chain, sigma-delta converter, sigma-delta modulation, switched capacitor filters},
	doi = {10.1109/SSMSD.2001.914956},
	author = {Gerosa, A. and Novo, A. and Neviani, A.}
}
@conference {876786,
	title = {Low-power sensing and digitization of cardiac signals based on sigma-delta conversion},
	booktitle = {Low Power Electronics and Design, 2000. ISLPED {\textquoteright}00. Proceedings of the 2000 International Symposium on},
	year = {2000},
	pages = {216 - 218},
	keywords = {0.8 micron, 2 muW, 2 V, 50 to 150 Hz, 8 kHz, cardiac signals, CMOS integrated circuits, CMOS technology, digitization, dynamic range, low-power circuits, low-power electronics, low-power sensing, medical signal processing, oversampled frequency, oversampling conversion techniques, pacemaker, pacemakers, power dissipation, sigma-delta conversion, sigma-delta modulation, signal sampling, switched networks, switched op-amp technique, third order modulator},
	doi = {10.1109/LPE.2000.155282},
	author = {Gerosa, A. and Novo, A. and Neviani, A.}
}
