@conference {7168918,
	title = {Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs},
	booktitle = {2015 IEEE International Symposium on Circuits and Systems (ISCAS)},
	year = {2015},
	month = {May},
	pages = {1454-1457},
	keywords = {Algorithm design and analysis, analog-to-digital converter, Clocks, CMOS digital integrated circuits, CMOS integrated circuits, CMOS technologies, CMOS technology, data weighted averaging, DEM algorithms, dynamic element matching algorithms, hardware complexity, Heuristic algorithms, internal DAC, logic design, mismatch cancellation, Modulation, multibit sigma-delta ADC, multibit ΣΔ ADC, Noise, optimal DWA design, sigma-delta modulation, sigma-delta modulator, size 65 nm, Timing, ΣΔ modulator},
	issn = {0271-4302},
	doi = {10.1109/ISCAS.2015.7168918},
	author = {A. Celin and Gerosa, A.}
}
@conference {1692653,
	title = {An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter},
	booktitle = {Proceedings of 2006 IEEE International Symposium on Circuits and Systems},
	year = {2006},
	pages = {4 pp.},
	keywords = {18.9 mW, 3G mobile communication, 4 bit, 4.6 mW, 5.5 mW, 7.4 mW, Bluetooth, cellular radio, flash converter, GSM, internal quantizer, multimode ADC, optimal architecture, power consumption, sigma-delta modulation, sigma-delta modulator, UMTS, wireless LAN, WLANa},
	doi = {10.1109/ISCAS.2006.1692653},
	author = {Gerosa, A. and Bevilacqua, A. and Neviani, A. and Xotta, A.}
}
