@article {4282067,
	title = {An Integrated Solution for Suppressing WLAN Signals in UWB Receivers},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {54},
	number = {8},
	year = {2007},
	pages = {1617 -1625},
	keywords = {bandwidth 4.9 GHz to 5.825 GHz, BiCMOS integrated circuit, BiCMOS integrated circuits, blocker filtering, frequency 3.6 GHz to 7.4 GHz, gain 22 dB to 19 dB, gain 5.5 dB to 8 dB, gain desensitization, interference suppression, intermodulation distortion, microwave receiver, microwave receivers, notch filter, notch filters, PCB connector, power 49.2 mW, power consumption, radio receivers, SiGe - Binary, size 0.35 micron, ultra wideband communication, ultrawide-band receiver, wireless LAN, wireless local area network transmission, WLAN signals},
	issn = {1549-8328},
	doi = {10.1109/TCSI.2007.902458},
	author = {Bevilacqua, A. and Maniero, A. and Gerosa, A. and Neviani, A.}
}
@conference {4099798,
	title = {A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO},
	booktitle = {Proceedings of the 32nd European Solid-State Circuits Conference},
	year = {2006},
	pages = {440 -443},
	keywords = {1 MHz, 1 mW, 3.4 to 7 GHz, dual-mode oscillator, phase noise, power consumption, resonators, transformer-based resonator, transformers, voltage-controlled oscillators, wideband VCO},
	issn = {1930-8833},
	doi = {10.1109/ESSCIR.2006.307475},
	author = {Bevilacqua, A. and Federico P. Pavan and Christoph Sandner and Gerosa, A. and Neviani, A.}
}
@conference {1692653,
	title = {An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter},
	booktitle = {Proceedings of 2006 IEEE International Symposium on Circuits and Systems},
	year = {2006},
	pages = {4 pp.},
	keywords = {18.9 mW, 3G mobile communication, 4 bit, 4.6 mW, 5.5 mW, 7.4 mW, Bluetooth, cellular radio, flash converter, GSM, internal quantizer, multimode ADC, optimal architecture, power consumption, sigma-delta modulation, sigma-delta modulator, UMTS, wireless LAN, WLANa},
	doi = {10.1109/ISCAS.2006.1692653},
	author = {Gerosa, A. and Bevilacqua, A. and Neviani, A. and Xotta, A.}
}
@conference {957696,
	title = {A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization},
	booktitle = {Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on},
	volume = {2},
	year = {2001},
	pages = {1099 -1102 vol.2},
	keywords = {0.35 micron, 0.35 mu, 300 MHz, 700 mW, analogue integrated circuits, anti-alias filter, bandwidth tunability, bit error rate, circuit bandwidth, CMOS memory circuits, CMOS technology, data rate, digital simulation, disc drives, equalisers, equalizer, fractionally spaced equalization, frequency errors, hard discs, hard disk drives, m, MATLAB, memory architecture, power consumption, pulse shaping circuits, pulse shaping precision, sampled data circuits, sampling phase, storage density, variable delay filter},
	doi = {10.1109/ICECS.2001.957696},
	author = {Gerosa, A. and Neviani, A. and Xotta, A. and Mian, G.A.}
}
@conference {813418,
	title = {A low complexity EPR-IV equalizer for hard disk read channels},
	booktitle = {Electronics, Circuits and Systems, 1999. Proceedings of ICECS {\textquoteright}99. The 6th IEEE International Conference on},
	volume = {2},
	year = {1999},
	pages = {1069 -1072 vol.2},
	keywords = {0.35 mum, ADC accuracy, analogue-digital conversion, area consumption, BRE, circuit design, circuit simulation, CMOS integrated circuits, complexity, digital post-processing, equalisers, equalization performance, FIR filters, fractionally spaced equalization, hard discs, hard disk read channels, low complexity EPR-IV equalizer, memory architecture, network synthesis, power consumption, sampled data, sampled data circuits, standard CMOS, transistor level simulation},
	doi = {10.1109/ICECS.1999.813418},
	author = {Gerosa, A. and Mian, G.A.}
}
