@article {704,
	title = {A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41\% Peak DE in 22 nm CMOS},
	journal = {IEEE Solid-State Circuits Letters},
	volume = {8},
	year = {2025},
	pages = {217 - 220},
	chapter = {217},
	keywords = {BLE, BT, Clocks, CMOS, Computer architecture, delays, Digital Doherty PA, Impedance, Microprocessors, Modulation, multi-class PA, power amplifiers, Power generation, SCPA, transmitters, uneven Doherty, Voltage},
	doi = {10.1109/LSSC.2025.3591570},
	author = {Fietta, Edoardo Baiesi and Seebacher, David and Ponton, Davide and Bevilacqua, A.}
}
@conference {718,
	title = {A DLL-Based FSK Demodulator for Asynchronous Communications},
	booktitle = {2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME)},
	year = {2025},
	keywords = {Asynchronous communication, asynchronous communications, Clocks, CMOS, CMOS technology, delaylocked loop, Demodulation, Frequency shift keying, frequency-shift keying (FSK), phase locked loops, Power demand, Semiconductor device modeling, Tracking loops, Wireless communication, wireline communication},
	doi = {10.1109/PRIME66228.2025.11203677},
	author = {Navarin, Lucrezia and Neviani, Andrea and Bevilacqua, A.}
}
